diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-28 01:32:48 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:32:15 +0300 |
| commit | d9b79ad275e7a98c566b3ac4b32950142d6bf9ad (patch) | |
| tree | 787a2885b7b78c60c71bb33345d61f09a7c3926b /drivers/gpu/drm/xe/regs/xe_regs.h | |
| parent | 7b829f6dd638c2cb45c7710bc7cd1d0395ea9bc1 (diff) | |
| download | linux-d9b79ad275e7a98c566b3ac4b32950142d6bf9ad.tar.xz | |
drm/xe: Drop gen afixes from registers
The defines for the registers were brought over from i915 while
bootstrapping the driver. As xe supports TGL and later only, it doesn't
make sense to keep the GEN* prefixes and suffixes in the registers: TGL
is graphics version 12, previously called "GEN12". So drop the prefix
everywhere.
v2:
- Also drop _TGL suffix and reword commit message as suggested
by Matt Roper. While at it, rename VSUNIT_CLKGATE_DIS_TGL to
VSUNIT_CLKGATE2_DIS with the additional "2", so it doesn't clash
with the define for the other register
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_regs.h | 41 |
1 files changed, 20 insertions, 21 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index c2a278b25fc9..50fc3c469086 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -11,23 +11,22 @@ #define LMEM_INIT REG_BIT(7) #define RENDER_RING_BASE 0x02000 -#define GEN11_BSD_RING_BASE 0x1c0000 -#define GEN11_BSD2_RING_BASE 0x1c4000 -#define GEN11_BSD3_RING_BASE 0x1d0000 -#define GEN11_BSD4_RING_BASE 0x1d4000 +#define BSD_RING_BASE 0x1c0000 +#define BSD2_RING_BASE 0x1c4000 +#define BSD3_RING_BASE 0x1d0000 +#define BSD4_RING_BASE 0x1d4000 #define XEHP_BSD5_RING_BASE 0x1e0000 #define XEHP_BSD6_RING_BASE 0x1e4000 #define XEHP_BSD7_RING_BASE 0x1f0000 #define XEHP_BSD8_RING_BASE 0x1f4000 -#define VEBOX_RING_BASE 0x1a000 -#define GEN11_VEBOX_RING_BASE 0x1c8000 -#define GEN11_VEBOX2_RING_BASE 0x1d8000 +#define VEBOX_RING_BASE 0x1c8000 +#define VEBOX2_RING_BASE 0x1d8000 #define XEHP_VEBOX3_RING_BASE 0x1e8000 #define XEHP_VEBOX4_RING_BASE 0x1f8000 -#define GEN12_COMPUTE0_RING_BASE 0x1a000 -#define GEN12_COMPUTE1_RING_BASE 0x1c000 -#define GEN12_COMPUTE2_RING_BASE 0x1e000 -#define GEN12_COMPUTE3_RING_BASE 0x26000 +#define COMPUTE0_RING_BASE 0x1a000 +#define COMPUTE1_RING_BASE 0x1c000 +#define COMPUTE2_RING_BASE 0x1e000 +#define COMPUTE3_RING_BASE 0x26000 #define BLT_RING_BASE 0x22000 #define XEHPC_BCS1_RING_BASE 0x3e0000 #define XEHPC_BCS2_RING_BASE 0x3e2000 @@ -43,8 +42,8 @@ #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) #define GT_RENDER_USER_INTERRUPT (1 << 0) -#define GEN7_FF_THREAD_MODE _MMIO(0x20a0) -#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) +#define FF_THREAD_MODE _MMIO(0x20a0) +#define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) #define PVC_RP_STATE_CAP _MMIO(0x281014) #define MTL_RP_STATE_CAP _MMIO(0x138000) @@ -86,18 +85,18 @@ #define DG1_MSTR_IRQ REG_BIT(31) #define DG1_MSTR_TILE(t) REG_BIT(t) -#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 -#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) +#define TIMESTAMP_OVERRIDE _MMIO(0x44074) +#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 +#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff +#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 +#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) #define GGC _MMIO(0x108040) #define GMS_MASK REG_GENMASK(15, 8) #define GGMS_MASK REG_GENMASK(7, 6) -#define GEN12_GSMBASE _MMIO(0x108100) -#define GEN12_DSMBASE _MMIO(0x1080C0) -#define GEN12_BDSM_MASK REG_GENMASK64(63, 20) +#define GSMBASE _MMIO(0x108100) +#define DSMBASE _MMIO(0x1080C0) +#define BDSM_MASK REG_GENMASK64(63, 20) #endif |