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authorMatt Roper <matthew.d.roper@intel.com>2023-06-02 00:52:25 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:34:14 +0300
commit876611c2b75689c6bea43bdbbbef9b358f71526a (patch)
tree9a5ac2da4dd0a51b434b21713c38796c25631f74 /drivers/gpu/drm/xe/tests/xe_bo.c
parentebd288cba7db7097ad50a4736ded94cb0d92fadf (diff)
downloadlinux-876611c2b75689c6bea43bdbbbef9b358f71526a.tar.xz
drm/xe: Memory allocations are tile-based, not GT-based
Since memory and address spaces are a tile concept rather than a GT concept, we need to plumb tile-based handling through lots of memory-related code. Note that one remaining shortcoming here that will need to be addressed before media GT support can be re-enabled is that although the address space is shared between a tile's GTs, each GT caches the PTEs independently in their own TLB and thus TLB invalidation should be handled at the GT level. v2: - Fix kunit test build. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20230601215244.678611-13-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/tests/xe_bo.c')
-rw-r--r--drivers/gpu/drm/xe/tests/xe_bo.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c
index 6235a6c73a06..f933e5df6c12 100644
--- a/drivers/gpu/drm/xe/tests/xe_bo.c
+++ b/drivers/gpu/drm/xe/tests/xe_bo.c
@@ -173,7 +173,7 @@ static int evict_test_run_gt(struct xe_device *xe, struct xe_gt *gt, struct kuni
{
struct xe_bo *bo, *external;
unsigned int bo_flags = XE_BO_CREATE_USER_BIT |
- XE_BO_CREATE_VRAM_IF_DGFX(gt);
+ XE_BO_CREATE_VRAM_IF_DGFX(gt_to_tile(gt));
struct xe_vm *vm = xe_migrate_get_vm(xe_device_get_root_tile(xe)->primary_gt.migrate);
struct ww_acquire_ctx ww;
int err, i;