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authorLucas De Marchi <lucas.demarchi@intel.com>2023-04-28 01:32:53 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:32:21 +0300
commit3512a78a3cefcd9ec0177771f637de0fe4a64ea2 (patch)
tree274f4114180aff907326184909eca50803f48563 /drivers/gpu/drm/xe/xe_ggtt.c
parent36e22be498fb8361ef411ac7d8cf9404338f6fc2 (diff)
downloadlinux-3512a78a3cefcd9ec0177771f637de0fe4a64ea2.tar.xz
drm/xe: Use XE_REG/XE_REG_MCR
These should replace the _MMIO() and MCR_REG() from i915, with the goal of being more extensible, allowing to pass the additional fields for struct xe_reg and struct xe_reg_mcr. Replace all uses of _MMIO() and MCR_REG() in xe. Since the RTP, reg-save-restore and WA infra are not ready to use the new type, just undef the macro like was done for the i915 types previously. That conversion will come later. v2: Remove MEDIA_SOFT_SCRATCH_COUNT/MEDIA_SOFT_SCRATCH re-added by mistake (Matt Roper) Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20230427223256.1432787-8-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_ggtt.c')
-rw-r--r--drivers/gpu/drm/xe/xe_ggtt.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index fc580d961dbb..4e5ad616063d 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -185,11 +185,11 @@ err:
return err;
}
-#define GUC_TLB_INV_CR _MMIO(0xcee8)
+#define GUC_TLB_INV_CR XE_REG(0xcee8)
#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0)
-#define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c)
+#define PVC_GUC_TLB_INV_DESC0 XE_REG(0xcf7c)
#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0)
-#define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80)
+#define PVC_GUC_TLB_INV_DESC1 XE_REG(0xcf80)
#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6)
void xe_ggtt_invalidate(struct xe_gt *gt)