diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-04-19 02:02:47 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:31:42 +0300 |
| commit | e881b1292f1791826476f1a2eaf80cc85e2677c5 (patch) | |
| tree | 5d8e4b6f9307b53af7c3f58f7bc5ef03ce67b92c /drivers/gpu/drm/xe/xe_ggtt.c | |
| parent | d33dc1dc29cab7871f9b0adee7b94b4dc5de5cb1 (diff) | |
| download | linux-e881b1292f1791826476f1a2eaf80cc85e2677c5.tar.xz | |
drm/xe: Drop GFX_FLSH_CNTL_GEN6 write during GGTT invalidation
The write of GFX_FLSH_CNTL_GEN6 was inherited from the i915 codebase
where it was used to force a flush of the write-combine buffer in cases
where the GSM/GGTT were mapped as WC. Since Xe never uses WC mappings
of the GGTT, this register write is unnecessary. Furthermore, this
register was removed on Xe_HP-based platforms, so this write winds up
clobbering an unrelated register.
v2:
- Also drop GFX_FLSH_CNTL_GEN6 from the register file now that it's no
longer used. (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230418230247.3802438-1-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_ggtt.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_ggtt.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c index 99bc9036c7a0..0fda9a18049b 100644 --- a/drivers/gpu/drm/xe/xe_ggtt.c +++ b/drivers/gpu/drm/xe/xe_ggtt.c @@ -196,11 +196,6 @@ void xe_ggtt_invalidate(struct xe_gt *gt) { /* TODO: vfunc for GuC vs. non-GuC */ - /* TODO: i915 makes comments about this being uncached and - * therefore flushing WC buffers. Is that really true here? - */ - xe_mmio_write32(gt, GFX_FLSH_CNTL_GEN6.reg, GFX_FLSH_CNTL_EN); - if (gt->uc.guc.submission_state.enabled) { int seqno; |