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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-10-16 19:34:52 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:43:00 +0300 |
| commit | e12a64881e97a78694012646cabd211399db8753 (patch) | |
| tree | 8d833c37958a332cd33dbd478f2f816106d7f08a /drivers/gpu/drm/xe/xe_gt.c | |
| parent | de54bb81d9d43d0b66a63d839963e9d359e0467d (diff) | |
| download | linux-e12a64881e97a78694012646cabd211399db8753.tar.xz | |
drm/xe: Separate number of registers from MI_LRI opcode
Keeping the number of registers to be loaded as a separate macro from
the instruction opcode will simplify some upcoming LRC parsing code.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-10-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_gt.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index c63e2e4750b1..a42ee3b9b8c7 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -145,7 +145,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) if (count) { xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name); - bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM(count); + bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); xa_for_each(&sr->xa, idx, entry) { struct xe_reg reg = entry->reg; |