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authorNiranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>2023-10-09 23:10:27 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-21 19:45:26 +0300
commit0d97ecce16bd26a1f90022cf0466ff15c4a0bd91 (patch)
tree54054df933f7fa114dc31f3f72b1b84ea73da897 /drivers/gpu/drm/xe/xe_gt_ccs_mode.h
parentb279b53015079bda2a311b48892dff362ac8ebc3 (diff)
downloadlinux-0d97ecce16bd26a1f90022cf0466ff15c4a0bd91.tar.xz
drm/xe: Enable Fixed CCS mode setting
Disable dynamic HW load balancing of compute resource assignment to engines and instead enabled fixed mode of mapping compute resources to engines on all platforms with more than one compute engine. By default enable only one CCS engine with all compute slices assigned to it. This is the desired configuration for common workloads. PVC platform supports only the fixed CCS mode (workaround 16016805146). v2: Rebase, make it platform agnostic v3: Minor code refactoring Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_gt_ccs_mode.h')
-rw-r--r--drivers/gpu/drm/xe/xe_gt_ccs_mode.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.h b/drivers/gpu/drm/xe/xe_gt_ccs_mode.h
new file mode 100644
index 000000000000..e8766879f6ec
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_GT_CCS_MODE_H_
+#define _XE_GT_CCS_MODE_H_
+
+#include "xe_device_types.h"
+#include "xe_gt.h"
+#include "xe_gt_types.h"
+#include "xe_platform_types.h"
+
+void xe_gt_apply_ccs_mode(struct xe_gt *gt);
+
+static inline bool xe_gt_ccs_mode_enabled(const struct xe_gt *gt)
+{
+ /* Check if there are more than one compute engines available */
+ return hweight32(CCS_MASK(gt)) > 1;
+}
+
+#endif
+