diff options
| author | Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> | 2023-09-29 08:15:39 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:42:08 +0300 |
| commit | 328e089bfb376a9817a260542fbea0fe9e0975ac (patch) | |
| tree | a396860a1803f01dd1462ad48bef1d9ee8adde0c /drivers/gpu/drm/xe/xe_hw_engine.c | |
| parent | 30603b5b0f8678fff799f4e3e2b45b8c08648575 (diff) | |
| download | linux-328e089bfb376a9817a260542fbea0fe9e0975ac.tar.xz | |
drm/xe: Leverage ComputeCS read L3 caching
On platforms that support read L3 caching, set the default mocs index in
CCS RING_CMD_CTL to leverage the read caching in L3.
Currently PVC and Xe2 platforms have the support.
Bspec: 72161
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230929051539.3157441-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_hw_engine.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_hw_engine.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index a8681089fb60..49128f640e15 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -316,22 +316,25 @@ static void hw_engine_setup_default_state(struct xe_hw_engine *hwe) { struct xe_gt *gt = hwe->gt; + struct xe_device *xe = gt_to_xe(gt); + /* + * RING_CMD_CCTL specifies the default MOCS entry that will be + * used by the command streamer when executing commands that + * don't have a way to explicitly specify a MOCS setting. + * The default should usually reference whichever MOCS entry + * corresponds to uncached behavior, although use of a WB cached + * entry is recommended by the spec in certain circumstances on + * specific platforms. + * Bspec: 72161 + */ const u8 mocs_write_idx = gt->mocs.uc_index; - /* TODO: missing handling of HAS_L3_CCS_READ platforms */ - const u8 mocs_read_idx = gt->mocs.uc_index; + const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && + (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ? + gt->mocs.wb_index : gt->mocs.uc_index; u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) | REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx); struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); const struct xe_rtp_entry_sr engine_entries[] = { - /* - * RING_CMD_CCTL specifies the default MOCS entry that will be - * used by the command streamer when executing commands that - * don't have a way to explicitly specify a MOCS setting. - * The default should usually reference whichever MOCS entry - * corresponds to uncached behavior, although use of a WB cached - * entry is recommended by the spec in certain circumstances on - * specific platforms. - */ { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED)), XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), |