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authorLinus Torvalds <torvalds@linux-foundation.org>2019-07-16 05:04:27 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2019-07-16 05:04:27 +0300
commitbe8454afc50f43016ca8b6130d9673bdd0bd56ec (patch)
tree897e49c1ccadeed9b083a3ffc13f0dd2d6d7d874 /drivers/gpu/ipu-v3
parentfec88ab0af9706b2201e5daf377c5031c62d11f7 (diff)
parent3729fe2bc2a01f4cc1aa88be8f64af06084c87d6 (diff)
downloadlinux-be8454afc50f43016ca8b6130d9673bdd0bd56ec.tar.xz
Merge tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "The biggest thing in this is the AMD Navi GPU support, this again contains a bunch of header files that are large. These are the new AMD RX5700 GPUs that just recently became available. New drivers: - ST-Ericsson MCDE driver - Ingenic JZ47xx SoC UAPI change: - HDR source metadata property Core: - HDR inforframes and EDID parsing - drm hdmi infoframe unpacking - remove prime sg_table caching into dma-buf - New gem vram helpers to reduce driver code - Lots of drmP.h removal - reservation fencing fix - documentation updates - drm_fb_helper_connector removed - mode name command handler rewrite fbcon: - Remove the fbcon notifiers ttm: - forward progress fixes dma-buf: - make mmap call optional - debugfs refcount fixes - dma-fence free with pending signals fix - each dma-buf gets an inode Panels: - Lots of additional panel bindings amdgpu: - initial navi10 support - avoid hw reset - HDR metadata support - new thermal sensors for vega asics - RAS fixes - use HMM rather than MMU notifier - xgmi topology via kfd - SR-IOV fixes - driver reload fixes - DC use a core bpc attribute - Aux fixes for DC - Bandwidth calc updates for DC - Clock handling refactor - kfd VEGAM support vmwgfx: - Coherent memory support changes i915: - HDR Support - HDMI i2c link - Icelake multi-segmented gamma support - GuC firmware update - Mule Creek Canyon PCH support for EHL - EHL platform updtes - move i915.alpha_support to i915.force_probe - runtime PM refactoring - VBT parsing refactoring - DSI fixes - struct mutex dependency reduction - GEM code reorg mali-dp: - Komeda driver features msm: - dsi vs EPROBE_DEFER fixes - msm8998 snapdragon 835 support - a540 gpu support - mdp5 and dpu interconnect support exynos: - drmP.h removal tegra: - misc fixes tda998x: - audio support improvements - pixel repeated mode support - quantisation range handling corrections - HDMI vendor info fix armada: - interlace support fix - overlay/video plane register handling refactor - add gamma support rockchip: - RX3328 support panfrost: - expose perf counters via hidden ioctls vkms: - enumerate CRC sources list ast: - rework BO handling mgag200: - rework BO handling dw-hdmi: - suspend/resume support rcar-du: - R8A774A1 Soc Support - LVDS dual-link mode support - Additional formats - Misc fixes omapdrm: - DSI command mode display support stm - fb modifier support - runtime PM support sun4i: - use vmap ops vc4: - binner bo binding rework v3d: - compute shader support - resync/sync fixes - job management refactoring lima: - NULL pointer in irq handler fix - scheduler default timeout virtio: - fence seqno support - trace events bochs: - misc fixes tc458767: - IRQ/HDP handling sii902x: - HDMI audio support atmel-hlcdc: - misc fixes meson: - zpos support" * tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm: (1815 commits) Revert "Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next" Revert "mm: adjust apply_to_pfn_range interface for dropped token." mm: adjust apply_to_pfn_range interface for dropped token. drm/amdgpu/navi10: add uclk activity sensor drm/amdgpu: properly guard the generic discovery code drm/amdgpu: add missing documentation on new module parameters drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback drm/amd/display: avoid 64-bit division drm/amdgpu/psp11: simplify the ucode register logic drm/amdgpu: properly guard DC support in navi code drm/amd/powerplay: vega20: fix uninitialized variable use drm/amd/display: dcn20: include linux/delay.h amdgpu: make pmu support optional drm/amd/powerplay: Zero initialize current_rpm in vega20_get_fan_speed_percent drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq drm/amd/powerplay: Use memset to initialize metrics structs drm/amdgpu/mes10.1: Fix header guard drm/amd/powerplay: add temperature sensor support for navi10 drm/amdgpu: fix scheduler timeout calc drm/amdgpu: Prepare for hmm_range_register API change (v2) ...
Diffstat (limited to 'drivers/gpu/ipu-v3')
-rw-r--r--drivers/gpu/ipu-v3/Makefile4
-rw-r--r--drivers/gpu/ipu-v3/ipu-ic-csc.c409
-rw-r--r--drivers/gpu/ipu-v3/ipu-ic.c138
-rw-r--r--drivers/gpu/ipu-v3/ipu-image-convert.c37
4 files changed, 482 insertions, 106 deletions
diff --git a/drivers/gpu/ipu-v3/Makefile b/drivers/gpu/ipu-v3/Makefile
index 7cc8b47e488b..5fe5ef20701a 100644
--- a/drivers/gpu/ipu-v3/Makefile
+++ b/drivers/gpu/ipu-v3/Makefile
@@ -2,8 +2,8 @@
obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o
imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-csi.o ipu-dc.o ipu-di.o \
- ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-image-convert.o \
- ipu-smfc.o ipu-vdi.o
+ ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-ic-csc.o \
+ ipu-image-convert.o ipu-smfc.o ipu-vdi.o
ifdef CONFIG_DRM
imx-ipu-v3-objs += ipu-pre.o ipu-prg.o
diff --git a/drivers/gpu/ipu-v3/ipu-ic-csc.c b/drivers/gpu/ipu-v3/ipu-ic-csc.c
new file mode 100644
index 000000000000..d1ca7ba94a12
--- /dev/null
+++ b/drivers/gpu/ipu-v3/ipu-ic-csc.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mentor Graphics Inc.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/sizes.h>
+#include "ipu-prv.h"
+
+#define QUANT_MAP(q) \
+ ((q) == V4L2_QUANTIZATION_FULL_RANGE || \
+ (q) == V4L2_QUANTIZATION_DEFAULT ? 0 : 1)
+
+/* identity matrix */
+static const struct ipu_ic_csc_params identity = {
+ .coeff = {
+ { 128, 0, 0, },
+ { 0, 128, 0, },
+ { 0, 0, 128, },
+ },
+ .offset = { 0, 0, 0, },
+ .scale = 2,
+};
+
+/*
+ * RGB full-range to RGB limited-range
+ *
+ * R_lim = 0.8588 * R_full + 16
+ * G_lim = 0.8588 * G_full + 16
+ * B_lim = 0.8588 * B_full + 16
+ */
+static const struct ipu_ic_csc_params rgbf2rgbl = {
+ .coeff = {
+ { 220, 0, 0, },
+ { 0, 220, 0, },
+ { 0, 0, 220, },
+ },
+ .offset = { 64, 64, 64, },
+ .scale = 1,
+};
+
+/*
+ * RGB limited-range to RGB full-range
+ *
+ * R_full = 1.1644 * (R_lim - 16)
+ * G_full = 1.1644 * (G_lim - 16)
+ * B_full = 1.1644 * (B_lim - 16)
+ */
+static const struct ipu_ic_csc_params rgbl2rgbf = {
+ .coeff = {
+ { 149, 0, 0, },
+ { 0, 149, 0, },
+ { 0, 0, 149, },
+ },
+ .offset = { -37, -37, -37, },
+ .scale = 2,
+};
+
+/*
+ * YUV full-range to YUV limited-range
+ *
+ * Y_lim = 0.8588 * Y_full + 16
+ * Cb_lim = 0.8784 * (Cb_full - 128) + 128
+ * Cr_lim = 0.8784 * (Cr_full - 128) + 128
+ */
+static const struct ipu_ic_csc_params yuvf2yuvl = {
+ .coeff = {
+ { 220, 0, 0, },
+ { 0, 225, 0, },
+ { 0, 0, 225, },
+ },
+ .offset = { 64, 62, 62, },
+ .scale = 1,
+ .sat = true,
+};
+
+/*
+ * YUV limited-range to YUV full-range
+ *
+ * Y_full = 1.1644 * (Y_lim - 16)
+ * Cb_full = 1.1384 * (Cb_lim - 128) + 128
+ * Cr_full = 1.1384 * (Cr_lim - 128) + 128
+ */
+static const struct ipu_ic_csc_params yuvl2yuvf = {
+ .coeff = {
+ { 149, 0, 0, },
+ { 0, 146, 0, },
+ { 0, 0, 146, },
+ },
+ .offset = { -37, -35, -35, },
+ .scale = 2,
+};
+
+static const struct ipu_ic_csc_params *rgb2rgb[] = {
+ &identity,
+ &rgbf2rgbl,
+ &rgbl2rgbf,
+ &identity,
+};
+
+static const struct ipu_ic_csc_params *yuv2yuv[] = {
+ &identity,
+ &yuvf2yuvl,
+ &yuvl2yuvf,
+ &identity,
+};
+
+/*
+ * BT.601 RGB full-range to YUV full-range
+ *
+ * Y = .2990 * R + .5870 * G + .1140 * B
+ * U = -.1687 * R - .3313 * G + .5000 * B + 128
+ * V = .5000 * R - .4187 * G - .0813 * B + 128
+ */
+static const struct ipu_ic_csc_params rgbf2yuvf_601 = {
+ .coeff = {
+ { 77, 150, 29, },
+ { -43, -85, 128, },
+ { 128, -107, -21, },
+ },
+ .offset = { 0, 512, 512, },
+ .scale = 1,
+};
+
+/* BT.601 RGB full-range to YUV limited-range */
+static const struct ipu_ic_csc_params rgbf2yuvl_601 = {
+ .coeff = {
+ { 66, 129, 25, },
+ { -38, -74, 112, },
+ { 112, -94, -18, },
+ },
+ .offset = { 64, 512, 512, },
+ .scale = 1,
+ .sat = true,
+};
+
+/* BT.601 RGB limited-range to YUV full-range */
+static const struct ipu_ic_csc_params rgbl2yuvf_601 = {
+ .coeff = {
+ { 89, 175, 34, },
+ { -50, -99, 149, },
+ { 149, -125, -24, },
+ },
+ .offset = { -75, 512, 512, },
+ .scale = 1,
+};
+
+/* BT.601 RGB limited-range to YUV limited-range */
+static const struct ipu_ic_csc_params rgbl2yuvl_601 = {
+ .coeff = {
+ { 77, 150, 29, },
+ { -44, -87, 131, },
+ { 131, -110, -21, },
+ },
+ .offset = { 0, 512, 512, },
+ .scale = 1,
+ .sat = true,
+};
+
+/*
+ * BT.601 YUV full-range to RGB full-range
+ *
+ * R = 1. * Y + 0 * (Cb - 128) + 1.4020 * (Cr - 128)
+ * G = 1. * Y - .3441 * (Cb - 128) - .7141 * (Cr - 128)
+ * B = 1. * Y + 1.7720 * (Cb - 128) + 0 * (Cr - 128)
+ *
+ * equivalently (factoring out the offsets):
+ *
+ * R = 1. * Y + 0 * Cb + 1.4020 * Cr - 179.456
+ * G = 1. * Y - .3441 * Cb - .7141 * Cr + 135.450
+ * B = 1. * Y + 1.7720 * Cb + 0 * Cr - 226.816
+ */
+static const struct ipu_ic_csc_params yuvf2rgbf_601 = {
+ .coeff = {
+ { 128, 0, 179, },
+ { 128, -44, -91, },
+ { 128, 227, 0, },
+ },
+ .offset = { -359, 271, -454, },
+ .scale = 2,
+};
+
+/* BT.601 YUV full-range to RGB limited-range */
+static const struct ipu_ic_csc_params yuvf2rgbl_601 = {
+ .coeff = {
+ { 110, 0, 154, },
+ { 110, -38, -78, },
+ { 110, 195, 0, },
+ },
+ .offset = { -276, 265, -358, },
+ .scale = 2,
+};
+
+/* BT.601 YUV limited-range to RGB full-range */
+static const struct ipu_ic_csc_params yuvl2rgbf_601 = {
+ .coeff = {
+ { 75, 0, 102, },
+ { 75, -25, -52, },
+ { 75, 129, 0, },
+ },
+ .offset = { -223, 136, -277, },
+ .scale = 3,
+};
+
+/* BT.601 YUV limited-range to RGB limited-range */
+static const struct ipu_ic_csc_params yuvl2rgbl_601 = {
+ .coeff = {
+ { 128, 0, 175, },
+ { 128, -43, -89, },
+ { 128, 222, 0, },
+ },
+ .offset = { -351, 265, -443, },
+ .scale = 2,
+};
+
+static const struct ipu_ic_csc_params *rgb2yuv_601[] = {
+ &rgbf2yuvf_601,
+ &rgbf2yuvl_601,
+ &rgbl2yuvf_601,
+ &rgbl2yuvl_601,
+};
+
+static const struct ipu_ic_csc_params *yuv2rgb_601[] = {
+ &yuvf2rgbf_601,
+ &yuvf2rgbl_601,
+ &yuvl2rgbf_601,
+ &yuvl2rgbl_601,
+};
+
+/*
+ * REC.709 encoding from RGB full range to YUV full range:
+ *
+ * Y = .2126 * R + .7152 * G + .0722 * B
+ * U = -.1146 * R - .3854 * G + .5000 * B + 128
+ * V = .5000 * R - .4542 * G - .0458 * B + 128
+ */
+static const struct ipu_ic_csc_params rgbf2yuvf_709 = {
+ .coeff = {
+ { 54, 183, 19 },
+ { -29, -99, 128 },
+ { 128, -116, -12 },
+ },
+ .offset = { 0, 512, 512 },
+ .scale = 1,
+};
+
+/* Rec.709 RGB full-range to YUV limited-range */
+static const struct ipu_ic_csc_params rgbf2yuvl_709 = {
+ .coeff = {
+ { 47, 157, 16, },
+ { -26, -87, 112, },
+ { 112, -102, -10, },
+ },
+ .offset = { 64, 512, 512, },
+ .scale = 1,
+ .sat = true,
+};
+
+/* Rec.709 RGB limited-range to YUV full-range */
+static const struct ipu_ic_csc_params rgbl2yuvf_709 = {
+ .coeff = {
+ { 63, 213, 22, },
+ { -34, -115, 149, },
+ { 149, -135, -14, },
+ },
+ .offset = { -75, 512, 512, },
+ .scale = 1,
+};
+
+/* Rec.709 RGB limited-range to YUV limited-range */
+static const struct ipu_ic_csc_params rgbl2yuvl_709 = {
+ .coeff = {
+ { 54, 183, 18, },
+ { -30, -101, 131, },
+ { 131, -119, -12, },
+ },
+ .offset = { 0, 512, 512, },
+ .scale = 1,
+ .sat = true,
+};
+
+/*
+ * Inverse REC.709 encoding from YUV full range to RGB full range:
+ *
+ * R = 1. * Y + 0 * (Cb - 128) + 1.5748 * (Cr - 128)
+ * G = 1. * Y - .1873 * (Cb - 128) - .4681 * (Cr - 128)
+ * B = 1. * Y + 1.8556 * (Cb - 128) + 0 * (Cr - 128)
+ *
+ * equivalently (factoring out the offsets):
+ *
+ * R = 1. * Y + 0 * Cb + 1.5748 * Cr - 201.574
+ * G = 1. * Y - .1873 * Cb - .4681 * Cr + 83.891
+ * B = 1. * Y + 1.8556 * Cb + 0 * Cr - 237.517
+ */
+static const struct ipu_ic_csc_params yuvf2rgbf_709 = {
+ .coeff = {
+ { 128, 0, 202 },
+ { 128, -24, -60 },
+ { 128, 238, 0 },
+ },
+ .offset = { -403, 168, -475 },
+ .scale = 2,
+};
+
+/* Rec.709 YUV full-range to RGB limited-range */
+static const struct ipu_ic_csc_params yuvf2rgbl_709 = {
+ .coeff = {
+ { 110, 0, 173, },
+ { 110, -21, -51, },
+ { 110, 204, 0, },
+ },
+ .offset = { -314, 176, -376, },
+ .scale = 2,
+};
+
+/* Rec.709 YUV limited-range to RGB full-range */
+static const struct ipu_ic_csc_params yuvl2rgbf_709 = {
+ .coeff = {
+ { 75, 0, 115, },
+ { 75, -14, -34, },
+ { 75, 135, 0, },
+ },
+ .offset = { -248, 77, -289, },
+ .scale = 3,
+};
+
+/* Rec.709 YUV limited-range to RGB limited-range */
+static const struct ipu_ic_csc_params yuvl2rgbl_709 = {
+ .coeff = {
+ { 128, 0, 197, },
+ { 128, -23, -59, },
+ { 128, 232, 0, },
+ },
+ .offset = { -394, 164, -464, },
+ .scale = 2,
+};
+
+static const struct ipu_ic_csc_params *rgb2yuv_709[] = {
+ &rgbf2yuvf_709,
+ &rgbf2yuvl_709,
+ &rgbl2yuvf_709,
+ &rgbl2yuvl_709,
+};
+
+static const struct ipu_ic_csc_params *yuv2rgb_709[] = {
+ &yuvf2rgbf_709,
+ &yuvf2rgbl_709,
+ &yuvl2rgbf_709,
+ &yuvl2rgbl_709,
+};
+
+static int calc_csc_coeffs(struct ipu_ic_csc *csc)
+{
+ const struct ipu_ic_csc_params **params_tbl;
+ int tbl_idx;
+
+ tbl_idx = (QUANT_MAP(csc->in_cs.quant) << 1) |
+ QUANT_MAP(csc->out_cs.quant);
+
+ if (csc->in_cs.cs == csc->out_cs.cs) {
+ csc->params = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ?
+ *yuv2yuv[tbl_idx] : *rgb2rgb[tbl_idx];
+
+ return 0;
+ }
+
+ /* YUV <-> RGB encoding is required */
+
+ switch (csc->out_cs.enc) {
+ case V4L2_YCBCR_ENC_601:
+ params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ?
+ yuv2rgb_601 : rgb2yuv_601;
+ break;
+ case V4L2_YCBCR_ENC_709:
+ params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ?
+ yuv2rgb_709 : rgb2yuv_709;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ csc->params = *params_tbl[tbl_idx];
+
+ return 0;
+}
+
+int __ipu_ic_calc_csc(struct ipu_ic_csc *csc)
+{
+ return calc_csc_coeffs(csc);
+}
+EXPORT_SYMBOL_GPL(__ipu_ic_calc_csc);
+
+int ipu_ic_calc_csc(struct ipu_ic_csc *csc,
+ enum v4l2_ycbcr_encoding in_enc,
+ enum v4l2_quantization in_quant,
+ enum ipu_color_space in_cs,
+ enum v4l2_ycbcr_encoding out_enc,
+ enum v4l2_quantization out_quant,
+ enum ipu_color_space out_cs)
+{
+ ipu_ic_fill_colorspace(&csc->in_cs, in_enc, in_quant, in_cs);
+ ipu_ic_fill_colorspace(&csc->out_cs, out_enc, out_quant, out_cs);
+
+ return __ipu_ic_calc_csc(csc);
+}
+EXPORT_SYMBOL_GPL(ipu_ic_calc_csc);
diff --git a/drivers/gpu/ipu-v3/ipu-ic.c b/drivers/gpu/ipu-v3/ipu-ic.c
index 89c3961f0fce..846461bac70d 100644
--- a/drivers/gpu/ipu-v3/ipu-ic.c
+++ b/drivers/gpu/ipu-v3/ipu-ic.c
@@ -140,8 +140,10 @@ struct ipu_ic {
const struct ic_task_regoffs *reg;
const struct ic_task_bitfields *bit;
- enum ipu_color_space in_cs, g_in_cs;
- enum ipu_color_space out_cs;
+ struct ipu_ic_colorspace in_cs;
+ struct ipu_ic_colorspace g_in_cs;
+ struct ipu_ic_colorspace out_cs;
+
bool graphics;
bool rotation;
bool in_use;
@@ -169,60 +171,11 @@ static inline void ipu_ic_write(struct ipu_ic *ic, u32 value, unsigned offset)
writel(value, ic->priv->base + offset);
}
-struct ic_csc_params {
- s16 coeff[3][3]; /* signed 9-bit integer coefficients */
- s16 offset[3]; /* signed 11+2-bit fixed point offset */
- u8 scale:2; /* scale coefficients * 2^(scale-1) */
- bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */
-};
-
-/*
- * Y = R * .299 + G * .587 + B * .114;
- * U = R * -.169 + G * -.332 + B * .500 + 128.;
- * V = R * .500 + G * -.419 + B * -.0813 + 128.;
- */
-static const struct ic_csc_params ic_csc_rgb2ycbcr = {
- .coeff = {
- { 77, 150, 29 },
- { 469, 427, 128 },
- { 128, 405, 491 },
- },
- .offset = { 0, 512, 512 },
- .scale = 1,
-};
-
-/* transparent RGB->RGB matrix for graphics combining */
-static const struct ic_csc_params ic_csc_rgb2rgb = {
- .coeff = {
- { 128, 0, 0 },
- { 0, 128, 0 },
- { 0, 0, 128 },
- },
- .scale = 2,
-};
-
-/*
- * R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
- * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
- * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
- */
-static const struct ic_csc_params ic_csc_ycbcr2rgb = {
- .coeff = {
- { 149, 0, 204 },
- { 149, 462, 408 },
- { 149, 255, 0 },
- },
- .offset = { -446, 266, -554 },
- .scale = 2,
-};
-
static int init_csc(struct ipu_ic *ic,
- enum ipu_color_space inf,
- enum ipu_color_space outf,
+ const struct ipu_ic_csc *csc,
int csc_index)
{
struct ipu_ic_priv *priv = ic->priv;
- const struct ic_csc_params *params;
u32 __iomem *base;
const u16 (*c)[3];
const u16 *a;
@@ -231,27 +184,16 @@ static int init_csc(struct ipu_ic *ic,
base = (u32 __iomem *)
(priv->tpmem_base + ic->reg->tpmem_csc[csc_index]);
- if (inf == IPUV3_COLORSPACE_YUV && outf == IPUV3_COLORSPACE_RGB)
- params = &ic_csc_ycbcr2rgb;
- else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_YUV)
- params = &ic_csc_rgb2ycbcr;
- else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_RGB)
- params = &ic_csc_rgb2rgb;
- else {
- dev_err(priv->ipu->dev, "Unsupported color space conversion\n");
- return -EINVAL;
- }
-
/* Cast to unsigned */
- c = (const u16 (*)[3])params->coeff;
- a = (const u16 *)params->offset;
+ c = (const u16 (*)[3])csc->params.coeff;
+ a = (const u16 *)csc->params.offset;
param = ((a[0] & 0x1f) << 27) | ((c[0][0] & 0x1ff) << 18) |
((c[1][1] & 0x1ff) << 9) | (c[2][2] & 0x1ff);
writel(param, base++);
- param = ((a[0] & 0x1fe0) >> 5) | (params->scale << 8) |
- (params->sat << 9);
+ param = ((a[0] & 0x1fe0) >> 5) | (csc->params.scale << 8) |
+ (csc->params.sat << 10);
writel(param, base++);
param = ((a[1] & 0x1f) << 27) | ((c[0][1] & 0x1ff) << 18) |
@@ -338,14 +280,14 @@ void ipu_ic_task_enable(struct ipu_ic *ic)
if (ic->rotation)
ic_conf |= ic->bit->ic_conf_rot_en;
- if (ic->in_cs != ic->out_cs)
+ if (ic->in_cs.cs != ic->out_cs.cs)
ic_conf |= ic->bit->ic_conf_csc1_en;
if (ic->graphics) {
ic_conf |= ic->bit->ic_conf_cmb_en;
ic_conf |= ic->bit->ic_conf_csc1_en;
- if (ic->g_in_cs != ic->out_cs)
+ if (ic->g_in_cs.cs != ic->out_cs.cs)
ic_conf |= ic->bit->ic_conf_csc2_en;
}
@@ -380,11 +322,12 @@ void ipu_ic_task_disable(struct ipu_ic *ic)
EXPORT_SYMBOL_GPL(ipu_ic_task_disable);
int ipu_ic_task_graphics_init(struct ipu_ic *ic,
- enum ipu_color_space in_g_cs,
+ const struct ipu_ic_colorspace *g_in_cs,
bool galpha_en, u32 galpha,
bool colorkey_en, u32 colorkey)
{
struct ipu_ic_priv *priv = ic->priv;
+ struct ipu_ic_csc csc2;
unsigned long flags;
u32 reg, ic_conf;
int ret = 0;
@@ -397,21 +340,36 @@ int ipu_ic_task_graphics_init(struct ipu_ic *ic,
ic_conf = ipu_ic_read(ic, IC_CONF);
if (!(ic_conf & ic->bit->ic_conf_csc1_en)) {
- /* need transparent CSC1 conversion */
- ret = init_csc(ic, IPUV3_COLORSPACE_RGB,
- IPUV3_COLORSPACE_RGB, 0);
+ struct ipu_ic_csc csc1;
+
+ ret = ipu_ic_calc_csc(&csc1,
+ V4L2_YCBCR_ENC_601,
+ V4L2_QUANTIZATION_FULL_RANGE,
+ IPUV3_COLORSPACE_RGB,
+ V4L2_YCBCR_ENC_601,
+ V4L2_QUANTIZATION_FULL_RANGE,
+ IPUV3_COLORSPACE_RGB);
if (ret)
goto unlock;
- }
-
- ic->g_in_cs = in_g_cs;
- if (ic->g_in_cs != ic->out_cs) {
- ret = init_csc(ic, ic->g_in_cs, ic->out_cs, 1);
+ /* need transparent CSC1 conversion */
+ ret = init_csc(ic, &csc1, 0);
if (ret)
goto unlock;
}
+ ic->g_in_cs = *g_in_cs;
+ csc2.in_cs = ic->g_in_cs;
+ csc2.out_cs = ic->out_cs;
+
+ ret = __ipu_ic_calc_csc(&csc2);
+ if (ret)
+ goto unlock;
+
+ ret = init_csc(ic, &csc2, 1);
+ if (ret)
+ goto unlock;
+
if (galpha_en) {
ic_conf |= IC_CONF_IC_GLB_LOC_A;
reg = ipu_ic_read(ic, IC_CMBP_1);
@@ -437,10 +395,9 @@ unlock:
EXPORT_SYMBOL_GPL(ipu_ic_task_graphics_init);
int ipu_ic_task_init_rsc(struct ipu_ic *ic,
+ const struct ipu_ic_csc *csc,
int in_width, int in_height,
int out_width, int out_height,
- enum ipu_color_space in_cs,
- enum ipu_color_space out_cs,
u32 rsc)
{
struct ipu_ic_priv *priv = ic->priv;
@@ -472,28 +429,23 @@ int ipu_ic_task_init_rsc(struct ipu_ic *ic,
ipu_ic_write(ic, rsc, ic->reg->rsc);
/* Setup color space conversion */
- ic->in_cs = in_cs;
- ic->out_cs = out_cs;
+ ic->in_cs = csc->in_cs;
+ ic->out_cs = csc->out_cs;
- if (ic->in_cs != ic->out_cs) {
- ret = init_csc(ic, ic->in_cs, ic->out_cs, 0);
- if (ret)
- goto unlock;
- }
+ ret = init_csc(ic, csc, 0);
-unlock:
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
int ipu_ic_task_init(struct ipu_ic *ic,
+ const struct ipu_ic_csc *csc,
int in_width, int in_height,
- int out_width, int out_height,
- enum ipu_color_space in_cs,
- enum ipu_color_space out_cs)
+ int out_width, int out_height)
{
- return ipu_ic_task_init_rsc(ic, in_width, in_height, out_width,
- out_height, in_cs, out_cs, 0);
+ return ipu_ic_task_init_rsc(ic, csc,
+ in_width, in_height,
+ out_width, out_height, 0);
}
EXPORT_SYMBOL_GPL(ipu_ic_task_init);
diff --git a/drivers/gpu/ipu-v3/ipu-image-convert.c b/drivers/gpu/ipu-v3/ipu-image-convert.c
index e744f3527ce1..9d25db6924b3 100644
--- a/drivers/gpu/ipu-v3/ipu-image-convert.c
+++ b/drivers/gpu/ipu-v3/ipu-image-convert.c
@@ -146,6 +146,7 @@ struct ipu_image_convert_ctx {
/* Source/destination image data and rotation mode */
struct ipu_image_convert_image in;
struct ipu_image_convert_image out;
+ struct ipu_ic_csc csc;
enum ipu_rotate_mode rot_mode;
u32 downsize_coeff_h;
u32 downsize_coeff_v;
@@ -1281,6 +1282,15 @@ static void init_idmac_channel(struct ipu_image_convert_ctx *ctx,
if (rot_mode)
ipu_cpmem_set_rotation(channel, rot_mode);
+ /*
+ * Skip writing U and V components to odd rows in the output
+ * channels for planar 4:2:0.
+ */
+ if ((channel == chan->out_chan ||
+ channel == chan->rotation_out_chan) &&
+ image->fmt->planar && image->fmt->uv_height_dec == 2)
+ ipu_cpmem_skip_odd_chroma_rows(channel);
+
if (channel == chan->rotation_in_chan ||
channel == chan->rotation_out_chan) {
burst_size = 8;
@@ -1310,7 +1320,6 @@ static int convert_start(struct ipu_image_convert_run *run, unsigned int tile)
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_image *s_image = &ctx->in;
struct ipu_image_convert_image *d_image = &ctx->out;
- enum ipu_color_space src_cs, dest_cs;
unsigned int dst_tile = ctx->out_tile_map[tile];
unsigned int dest_width, dest_height;
unsigned int col, row;
@@ -1320,9 +1329,6 @@ static int convert_start(struct ipu_image_convert_run *run, unsigned int tile)
dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n",
__func__, chan->ic_task, ctx, run, tile, dst_tile);
- src_cs = ipu_pixelformat_to_colorspace(s_image->fmt->fourcc);
- dest_cs = ipu_pixelformat_to_colorspace(d_image->fmt->fourcc);
-
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
/* swap width/height for resizer */
dest_width = d_image->tile[dst_tile].height;
@@ -1345,13 +1351,12 @@ static int convert_start(struct ipu_image_convert_run *run, unsigned int tile)
s_image->tile[tile].height, dest_width, dest_height, rsc);
/* setup the IC resizer and CSC */
- ret = ipu_ic_task_init_rsc(chan->ic,
- s_image->tile[tile].width,
- s_image->tile[tile].height,
- dest_width,
- dest_height,
- src_cs, dest_cs,
- rsc);
+ ret = ipu_ic_task_init_rsc(chan->ic, &ctx->csc,
+ s_image->tile[tile].width,
+ s_image->tile[tile].height,
+ dest_width,
+ dest_height,
+ rsc);
if (ret) {
dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret);
return ret;
@@ -2063,6 +2068,16 @@ ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
calc_tile_resize_coefficients(ctx);
+ ret = ipu_ic_calc_csc(&ctx->csc,
+ s_image->base.pix.ycbcr_enc,
+ s_image->base.pix.quantization,
+ ipu_pixelformat_to_colorspace(s_image->fmt->fourcc),
+ d_image->base.pix.ycbcr_enc,
+ d_image->base.pix.quantization,
+ ipu_pixelformat_to_colorspace(d_image->fmt->fourcc));
+ if (ret)
+ goto out_free;
+
dump_format(ctx, s_image);
dump_format(ctx, d_image);