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authorJames Clark <james.clark@arm.com>2022-03-04 20:19:00 +0300
committerMathieu Poirier <mathieu.poirier@linaro.org>2022-04-13 20:04:28 +0300
commitf4d1f2142a608667a1849894b48b9c6e3343210c (patch)
tree87f7779c77ac3e3fab69a8ad6072fddbb57ed8cf /drivers/hwtracing/coresight/coresight-etm4x.h
parentcf0c7f18d30eb9bba44ac04a87fef5035953b283 (diff)
downloadlinux-f4d1f2142a608667a1849894b48b9c6e3343210c.tar.xz
coresight: etm4x: Cleanup TRCIDR3 register accesses
This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-4-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-etm4x.h')
-rw-r--r--drivers/hwtracing/coresight/coresight-etm4x.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index cfdf966016b7..1b95c63938f0 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -147,6 +147,16 @@
#define TRCIDR2_VMIDSIZE_MASK GENMASK(14, 10)
#define TRCIDR2_CCSIZE_MASK GENMASK(28, 25)
+#define TRCIDR3_CCITMIN_MASK GENMASK(11, 0)
+#define TRCIDR3_EXLEVEL_S_MASK GENMASK(19, 16)
+#define TRCIDR3_EXLEVEL_NS_MASK GENMASK(23, 20)
+#define TRCIDR3_TRCERR BIT(24)
+#define TRCIDR3_SYNCPR BIT(25)
+#define TRCIDR3_STALLCTL BIT(26)
+#define TRCIDR3_SYSSTALL BIT(27)
+#define TRCIDR3_NUMPROC_LO_MASK GENMASK(30, 28)
+#define TRCIDR3_NUMPROC_HI_MASK GENMASK(13, 12)
+#define TRCIDR3_NOOVERFLOW BIT(31)
/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions