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authorJames Clark <james.clark@arm.com>2022-03-04 20:18:58 +0300
committerMathieu Poirier <mathieu.poirier@linaro.org>2022-04-13 20:04:08 +0300
commite601cc9a3a9b94b48de7f120b583d94c2d9fe3b5 (patch)
tree6a62e9bc90aa7e89f875d6c88dfb30c7446a22a0 /drivers/hwtracing/coresight/coresight-etm4x.h
parentce522ba9ef7e2d9fb22a39eb3371c0c64e2a433e (diff)
downloadlinux-e601cc9a3a9b94b48de7f120b583d94c2d9fe3b5.tar.xz
coresight: etm4x: Cleanup TRCIDR0 register accesses
This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Link: https://lore.kernel.org/r/20220304171913.2292458-2-james.clark@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-etm4x.h')
-rw-r--r--drivers/hwtracing/coresight/coresight-etm4x.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 3c4d69b096ca..300741fbc0de 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -131,6 +131,19 @@
#define TRCRSR_TA BIT(12)
/*
+ * Bit positions of registers that are defined above, in the sysreg.h style
+ * of _MASK for multi bit fields and BIT() for single bits.
+ */
+#define TRCIDR0_INSTP0_MASK GENMASK(2, 1)
+#define TRCIDR0_TRCBB BIT(5)
+#define TRCIDR0_TRCCOND BIT(6)
+#define TRCIDR0_TRCCCI BIT(7)
+#define TRCIDR0_RETSTACK BIT(9)
+#define TRCIDR0_NUMEVENT_MASK GENMASK(11, 10)
+#define TRCIDR0_QSUPP_MASK GENMASK(16, 15)
+#define TRCIDR0_TSSIZE_MASK GENMASK(28, 24)
+
+/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
*/