diff options
author | Anshuman Khandual <anshuman.khandual@arm.com> | 2023-06-14 09:59:39 +0300 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-06-14 16:37:33 +0300 |
commit | 7bb948826610f05b42567ce89156d6513d53d988 (patch) | |
tree | ecbb5c8d9fd616f246569a2bdf4ace6d7d8e89d1 /drivers/hwtracing/coresight/coresight-trbe.c | |
parent | 90cdde836c43154acb474553095bb7ee741160a5 (diff) | |
download | linux-7bb948826610f05b42567ce89156d6513d53d988.tar.xz |
arm64/sysreg: Rename TRBSR_EL1 fields per auto-gen tools format
This renames TRBSR_EL1 register fields per auto-gen tools format without
causing any functional change in the TRBE driver.
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: kvmarm@lists.linux.dev
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-5-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-trbe.c')
-rw-r--r-- | drivers/hwtracing/coresight/coresight-trbe.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 1d9d141c62e9..1bab91ce8e95 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -582,12 +582,12 @@ static void clr_trbe_status(void) u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1); WARN_ON(is_trbe_enabled()); - trbsr &= ~TRBSR_IRQ; - trbsr &= ~TRBSR_TRG; - trbsr &= ~TRBSR_WRAP; - trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT); - trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT); - trbsr &= ~TRBSR_STOP; + trbsr &= ~TRBSR_EL1_IRQ; + trbsr &= ~TRBSR_EL1_TRG; + trbsr &= ~TRBSR_EL1_WRAP; + trbsr &= ~TRBSR_EL1_EC_MASK; + trbsr &= ~TRBSR_EL1_BSC_MASK; + trbsr &= ~TRBSR_EL1_S; write_sysreg_s(trbsr, SYS_TRBSR_EL1); } |