diff options
| author | Alexander Shishkin <alexander.shishkin@linux.intel.com> | 2016-02-15 20:11:55 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-02-21 01:09:14 +0300 |
| commit | 4d02ceff32f35f3ea745be6114503c2d2505da99 (patch) | |
| tree | 8e4aaa8c266e4cac18b6902bff3022d0c0fea297 /drivers/hwtracing/intel_th/gth.c | |
| parent | c1a327c4d3d7d2ce2c75e77fcfd34a729ab45f6f (diff) | |
| download | linux-4d02ceff32f35f3ea745be6114503c2d2505da99.tar.xz | |
intel_th: Update scratchpad bits according to enabled output activity
Intel TH implements a scratchpad register to indicate to the firmware
and external debuggers what trace configuration is enabled so that
everybody plays nicely together. The register is a bit field and the
bit assignment convention is described in the developer's manual.
This patch enables the driver to automatically set scratchpad register
bits according to the output configuration that's enabled.
Based on work by Yann Fouassier.
Signed-off-by: Yann Fouassier <yann.fouassier@intel.com>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing/intel_th/gth.c')
| -rw-r--r-- | drivers/hwtracing/intel_th/gth.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/hwtracing/intel_th/gth.c b/drivers/hwtracing/intel_th/gth.c index e4c9811c1f40..9beea0b54231 100644 --- a/drivers/hwtracing/intel_th/gth.c +++ b/drivers/hwtracing/intel_th/gth.c @@ -286,6 +286,10 @@ static int intel_th_gth_reset(struct gth_device *gth) if (scratchpad & SCRPD_DEBUGGER_IN_USE) return -EBUSY; + /* Always save/restore STH and TU registers in S0ix entry/exit */ + scratchpad |= SCRPD_STH_IS_ENABLED | SCRPD_TRIGGER_IS_ENABLED; + iowrite32(scratchpad, gth->base + REG_GTH_SCRPD0); + /* output ports */ for (port = 0; port < 8; port++) { if (gth_output_parm_get(gth, port, TH_OUTPUT_PARM(port)) == @@ -488,6 +492,10 @@ static void intel_th_gth_disable(struct intel_th_device *thdev, if (!count) dev_dbg(&thdev->dev, "timeout waiting for GTH[%d] PLE\n", output->port); + + reg = ioread32(gth->base + REG_GTH_SCRPD0); + reg &= ~output->scratchpad; + iowrite32(reg, gth->base + REG_GTH_SCRPD0); } /** @@ -502,7 +510,7 @@ static void intel_th_gth_enable(struct intel_th_device *thdev, struct intel_th_output *output) { struct gth_device *gth = dev_get_drvdata(&thdev->dev); - u32 scr = 0xfc0000; + u32 scr = 0xfc0000, scrpd; int master; spin_lock(>h->gth_lock); @@ -517,6 +525,10 @@ static void intel_th_gth_enable(struct intel_th_device *thdev, output->active = true; spin_unlock(>h->gth_lock); + scrpd = ioread32(gth->base + REG_GTH_SCRPD0); + scrpd |= output->scratchpad; + iowrite32(scrpd, gth->base + REG_GTH_SCRPD0); + iowrite32(scr, gth->base + REG_GTH_SCR); iowrite32(0, gth->base + REG_GTH_SCR2); } |