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authorBjorn Helgaas <bhelgaas@google.com>2018-08-15 22:59:06 +0300
committerBjorn Helgaas <bhelgaas@google.com>2018-08-15 22:59:06 +0300
commit3a48dc6fc260c9cac302a9ffaeab95359431c485 (patch)
tree7dc85ea850ef81c756b55e2bdec5b7b6146f535e /drivers/infiniband/hw/hfi1/pcie.c
parente7aaf90f9d9dbbba54f67c653a1c56c2bf117268 (diff)
parent7695e73f3db4576ef3ce05063c28e9a673425763 (diff)
downloadlinux-3a48dc6fc260c9cac302a9ffaeab95359431c485.tar.xz
Merge branch 'pci/virtualization'
- To avoid bus errors, enable PASID only if entire path supports End-End TLP prefixes (Sinan Kaya) - Unify slot and bus reset functions and remove hotplug knowledge from callers (Sinan Kaya) - Add Function-Level Reset quirks for Intel and Samsung NVMe devices to fix guest reboot issues (Alex Williamson) - Add function 1 DMA alias quirk for Marvell 88SS9183 PCIe SSD Controller (Bjorn Helgaas) * pci/virtualization: PCI: Add function 1 DMA alias quirk for Marvell 88SS9183 PCI: Delay after FLR of Intel DC P3700 NVMe PCI: Disable Samsung SM961/PM961 NVMe before FLR PCI: Export pcie_has_flr() PCI: Rename pci_try_reset_bus() to pci_reset_bus() PCI: Deprecate pci_reset_bus() and pci_reset_slot() functions PCI: Unify try slot and bus reset API PCI: Hide pci_reset_bridge_secondary_bus() from drivers IB/hfi1: Use pci_try_reset_bus() for initiating PCI Secondary Bus Reset PCI: Handle error return from pci_reset_bridge_secondary_bus() PCI/IOV: Tidy pci_sriov_set_totalvfs() PCI: Enable PASID only if entire path supports End-End TLP prefixes # Conflicts: # drivers/pci/hotplug/pciehp_hpc.c
Diffstat (limited to 'drivers/infiniband/hw/hfi1/pcie.c')
-rw-r--r--drivers/infiniband/hw/hfi1/pcie.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index 4d4371bf2c7c..baf7c324f7b8 100644
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -905,9 +905,7 @@ static int trigger_sbr(struct hfi1_devdata *dd)
* delay after a reset is required. Per spec requirements,
* the link is either working or not after that point.
*/
- pci_reset_bridge_secondary_bus(dev->bus->self);
-
- return 0;
+ return pci_reset_bus(dev);
}
/*