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| author | Jason Gunthorpe <jgg@nvidia.com> | 2020-11-15 14:43:11 +0300 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2020-11-16 23:53:30 +0300 |
| commit | 8a7904a672a1d33c848e5129f886ee69e0773a2e (patch) | |
| tree | d8cb36bb7a7da1682f46adac04f7aa36b205276e /drivers/infiniband/hw/mlx5/srq.h | |
| parent | 878f7b31c3a7f3e48c6601ea373b8688e7e308e0 (diff) | |
| download | linux-8a7904a672a1d33c848e5129f886ee69e0773a2e.tar.xz | |
RDMA/mlx5: Lower setting the umem's PAS for SRQ
Some of the SRQ types are created using a WQ, and the WQ requires a
different parameter set to mlx5_umem_find_best_quantized_pgoff() as it has
a 5 bit page_offset.
Add the umem to the mlx5_srq_attr and defer computing the PAS data until
the code has figured out what kind of mailbox to use. Compute the PAS
directly from the umem for each of the four unique mailbox types.
This also avoids allocating memory to store the user PAS, instead it is
written directly to the mailbox as in most other cases.
Fixes: 01949d0109ee ("net/mlx5_core: Enable XRCs and SRQs when using ISSI > 0")
Link: https://lore.kernel.org/r/20201115114311.136250-8-leon@kernel.org
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/infiniband/hw/mlx5/srq.h')
| -rw-r--r-- | drivers/infiniband/hw/mlx5/srq.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/mlx5/srq.h b/drivers/infiniband/hw/mlx5/srq.h index 2c3627b2509d..a7e3dc5564ac 100644 --- a/drivers/infiniband/hw/mlx5/srq.h +++ b/drivers/infiniband/hw/mlx5/srq.h @@ -28,6 +28,7 @@ struct mlx5_srq_attr { u32 user_index; u64 db_record; __be64 *pas; + struct ib_umem *umem; u32 tm_log_list_size; u32 tm_next_tag; u32 tm_hw_phase_cnt; |