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authorRoland Dreier <rolandd@cisco.com>2008-12-31 02:30:26 +0300
committerRoland Dreier <rolandd@cisco.com>2008-12-31 02:30:26 +0300
commitf781a22fa2ec11878a960bc3c2abb0a76f9a8f16 (patch)
tree730299e58bb709ed21977270389521c295911ac8 /drivers/infiniband
parent541ef5cbb8e68189d47272cea52a69abc30259bc (diff)
downloadlinux-f781a22fa2ec11878a960bc3c2abb0a76f9a8f16.tar.xz
IB/mlx4: Fix reading SL field out of cqe->sl_vid
Commit f780a9f1 ("mlx4_core: Add ethernet fields to CQE struct") introduced a bug in how wc->sl is set in mlx4_ib_poll_one() -- since cqe->sl_vid is a big-endian value, the shift must be done after converting to host endianness. This bug was found using sparse endianness checking. Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r--drivers/infiniband/hw/mlx4/cq.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c
index 8415ecce5c4c..a3c5af1d7ec0 100644
--- a/drivers/infiniband/hw/mlx4/cq.c
+++ b/drivers/infiniband/hw/mlx4/cq.c
@@ -699,7 +699,7 @@ repoll:
}
wc->slid = be16_to_cpu(cqe->rlid);
- wc->sl = be16_to_cpu(cqe->sl_vid >> 12);
+ wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
wc->src_qp = g_mlpath_rqpn & 0xffffff;
wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;