diff options
| author | Robin Murphy <robin.murphy@arm.com> | 2019-10-25 21:08:37 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-01-10 18:39:23 +0300 |
| commit | d1e5f26f14272b5039cc198569ec4fabed14e6db (patch) | |
| tree | 356c25d1b1762b46f6572573aff0e67a557dd4b6 /drivers/iommu/msm_iommu.c | |
| parent | cd037ff2f98227148002084d588f03b348469fe4 (diff) | |
| download | linux-d1e5f26f14272b5039cc198569ec4fabed14e6db.tar.xz | |
iommu/io-pgtable-arm: Rationalise TTBRn handling
TTBR1 values have so far been redundant since no users implement any
support for split address spaces. Crucially, though, one of the main
reasons for wanting to do so is to be able to manage each half entirely
independently, e.g. context-switching one set of mappings without
disturbing the other. Thus it seems unlikely that tying two tables
together in a single io_pgtable_cfg would ever be particularly desirable
or useful.
Streamline the configs to just a single conceptual TTBR value
representing the allocated table. This paves the way for future users to
support split address spaces by simply allocating a table and dealing
with the detailed TTBRn logistics themselves.
Tested-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
[will: Drop change to ttbr value]
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu/msm_iommu.c')
| -rw-r--r-- | drivers/iommu/msm_iommu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 93f14bca26ee..94a6df1bddd6 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -279,8 +279,8 @@ static void __program_context(void __iomem *base, int ctx, SET_V2PCFG(base, ctx, 0x3); SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); - SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); - SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); + SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); + SET_TTBR1(base, ctx, 0); /* Set prrr and nmrr */ SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); |