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authorThomas Gleixner <tglx@linutronix.de>2014-06-20 01:34:40 +0400
committerJason Cooper <jason@lakedaemon.net>2014-06-24 16:37:42 +0400
commit03319a1a2966ec39be79182d6d529221c38fde72 (patch)
treef83eb0faf71112039968cd76366cbe8024a8878d /drivers/irqchip/spear-shirq.c
parentc5d1d857482b080875640bb68bc9d8b65ad29b6f (diff)
downloadlinux-03319a1a2966ec39be79182d6d529221c38fde72.tar.xz
irqchip: spear_shirq: Reorder the spear320 ras blocks
Order the ras blocks in the order of interrupts not alphabetically. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20140619212713.310591579@linutronix.de Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'drivers/irqchip/spear-shirq.c')
-rw-r--r--drivers/irqchip/spear-shirq.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c
index f7c25a77845a..7ebb1a2fbfc7 100644
--- a/drivers/irqchip/spear-shirq.c
+++ b/drivers/irqchip/spear-shirq.c
@@ -138,20 +138,22 @@ static struct spear_shirq *spear310_shirq_blocks[] = {
#define SPEAR320_INT_CLR_MASK_REG 0x04
#define SPEAR320_INT_ENB_MASK_REG 0x08
-static struct spear_shirq spear320_shirq_ras1 = {
- .offset = 7,
- .nr_irqs = 3,
+static struct spear_shirq spear320_shirq_ras3 = {
+ .offset = 0,
+ .nr_irqs = 7,
+ .disabled = 1,
.regs = {
- .enb_reg = -1,
+ .enb_reg = SPEAR320_INT_ENB_MASK_REG,
+ .reset_to_enb = 1,
.status_reg = SPEAR320_INT_STS_MASK_REG,
.clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
-static struct spear_shirq spear320_shirq_ras2 = {
- .offset = 10,
- .nr_irqs = 1,
+static struct spear_shirq spear320_shirq_ras1 = {
+ .offset = 7,
+ .nr_irqs = 3,
.regs = {
.enb_reg = -1,
.status_reg = SPEAR320_INT_STS_MASK_REG,
@@ -160,13 +162,11 @@ static struct spear_shirq spear320_shirq_ras2 = {
},
};
-static struct spear_shirq spear320_shirq_ras3 = {
- .offset = 0,
- .nr_irqs = 7,
- .disabled = 1,
+static struct spear_shirq spear320_shirq_ras2 = {
+ .offset = 10,
+ .nr_irqs = 1,
.regs = {
- .enb_reg = SPEAR320_INT_ENB_MASK_REG,
- .reset_to_enb = 1,
+ .enb_reg = -1,
.status_reg = SPEAR320_INT_STS_MASK_REG,
.clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,