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author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-02-24 20:47:43 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-02-24 20:47:43 +0300 |
commit | b817c931233b24129ac8d2c858669ee656a473dd (patch) | |
tree | 719e0cf74ba30cda7f6448e744606e12108ac149 /drivers/mailbox/sprd-mailbox.c | |
parent | 825d1508750c0cad13e5da564d47a6d59c7612d6 (diff) | |
parent | 6b50df2b8c208a04d44b8df5b7baaf668ceb8fc3 (diff) | |
download | linux-b817c931233b24129ac8d2c858669ee656a473dd.tar.xz |
Merge tag 'mailbox-v5.12' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar:
- sprd: fix a macro value
- omap: support for K3 AM64x
- tegra: fix lockdep warnings
- qcom: support for SDX55 and SC8180X
- arm: fixes for sparse, kfree and void return
* tag 'mailbox-v5.12' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
mailbox: arm_mhuv2: Skip calling kfree() with invalid pointer
mailbox: tegra-hsp: Set lockdep class dynamically
mailbox: sprd: correct definition of SPRD_OUTBOX_FIFO_FULL
mailbox: arm_mhuv2: make remove callback return void
mailbox: arm_mhuv2: Fix sparse warnings
mailbox: qcom: Add support for SDX55 APCS IPC
dt-bindings: mailbox: Add binding for SDX55 APCS
mailbox: omap: Add support for K3 AM64x SoCs
dt-bindings: mailbox: omap: Update binding for AM64x SoCs
mailbox: qcom: Add SC8180X apcs compatible
dt-bindings: mailbox: qcom: Add SC8180X APCS compatible
Diffstat (limited to 'drivers/mailbox/sprd-mailbox.c')
-rw-r--r-- | drivers/mailbox/sprd-mailbox.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mailbox/sprd-mailbox.c b/drivers/mailbox/sprd-mailbox.c index f6fab24ae8a9..4c325301a2fe 100644 --- a/drivers/mailbox/sprd-mailbox.c +++ b/drivers/mailbox/sprd-mailbox.c @@ -35,7 +35,7 @@ #define SPRD_MBOX_IRQ_CLR BIT(0) /* Bit and mask definiation for outbox's SPRD_MBOX_FIFO_STS register */ -#define SPRD_OUTBOX_FIFO_FULL BIT(0) +#define SPRD_OUTBOX_FIFO_FULL BIT(2) #define SPRD_OUTBOX_FIFO_WR_SHIFT 16 #define SPRD_OUTBOX_FIFO_RD_SHIFT 24 #define SPRD_OUTBOX_FIFO_POS_MASK GENMASK(7, 0) |