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| author | Paul Elder <paul.elder@ideasonboard.com> | 2024-02-16 12:54:57 +0300 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2024-02-23 15:23:32 +0300 |
| commit | 6c144351f2366c590336cc6c23918e20c43ef938 (patch) | |
| tree | ca1c026b22ecead966f5b151fbf094a6fbc99f42 /drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h | |
| parent | 0a593f711ac7fb775ac132e9f5fea54ae2a0d85d (diff) | |
| download | linux-6c144351f2366c590336cc6c23918e20c43ef938.tar.xz | |
media: rkisp1: Fix endianness on raw streams on i.MX8MP
The i.MX8MP has extra register fields in the memory interface control
register for setting the output format, which work with the output
alignment format register for byte-swapping and LSB/MSB alignment.
With processed and 8-bit raw streams, it doesn't cause any problems to
not set these, but with raw streams of higher bit depth the endianness
is swapped and the data is not aligned properly.
Add support for setting these registers and plumb them in to fix this.
While at it, reflow a comment related to the forced configuration
update.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Diffstat (limited to 'drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h')
| -rw-r--r-- | drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h index 3b19c8411360..fccf4c17ee8d 100644 --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h @@ -144,6 +144,15 @@ /* MI_INIT */ #define RKISP1_CIF_MI_INIT_SKIP BIT(2) #define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5) +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_MASK (15 << 5) /* MI_CTRL_SHD */ #define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0) |