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authorOfir Bitton <obitton@habana.ai>2020-11-08 14:10:09 +0300
committerOded Gabbay <ogabbay@kernel.org>2020-11-30 11:47:34 +0300
commitd611b9f0b199ebfaca78ec4205a889831fdd45cd (patch)
tree83c8372670a47300eb04fcfd880bc7dbd34da141 /drivers/misc/habanalabs/include/common/hl_boot_if.h
parent7f070c913c361ed79dd29d9256b486b1b105d7f0 (diff)
downloadlinux-d611b9f0b199ebfaca78ec4205a889831fdd45cd.tar.xz
habanalabs: fetch hard reset capability from FW
Driver must fetch FW hard reset capability during boot time, in order to skip the hard reset flow if necessary. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/include/common/hl_boot_if.h')
-rw-r--r--drivers/misc/habanalabs/include/common/hl_boot_if.h30
1 files changed, 19 insertions, 11 deletions
diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h
index d928ad93cd80..60916780df35 100644
--- a/drivers/misc/habanalabs/include/common/hl_boot_if.h
+++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h
@@ -84,45 +84,52 @@
* device is indicated as security enabled,
* registers are protected, and device
* uses keys for image verification.
- * Initialized at: preboot
+ * Initialized in: preboot
*
* CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled.
* Enabled when JTAG or DEBUG is enabled
* in FW.
- * Initialized at: preboot
+ * Initialized in: preboot
*
* CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled.
* Watchdog is enabled in FW.
- * Initialized at: preboot
+ * Initialized in: preboot
*
* CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled.
* DRAM initialization has been done in FW.
- * Initialized at: u-boot
+ * Initialized in: u-boot
*
* CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled.
* If set, it means that during boot,
* FW waited for BMC data.
- * Initialized at: u-boot
+ * Initialized in: u-boot
*
* CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized.
* FW initialized E2E credits.
- * Initialized at: u-boot
+ * Initialized in: u-boot
*
* CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized.
* FW initialized HBM credits.
- * Initialized at: u-boot
+ * Initialized in: u-boot
*
* CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized.
* FW initialized rate limiter.
- * Initialized at: u-boot
+ * Initialized in: u-boot
*
* CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled.
* FW initialized SRAM scrambler.
- * Initialized at: linux
+ * Initialized in: linux
*
* CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled.
* FW initialized DRAM scrambler.
- * Initialized at: u-boot
+ * Initialized in: u-boot
+ *
+ * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled.
+ * FW has the hard reset procedure
+ * implemented. This means that FW will
+ * perform hard reset procedure on
+ * receiving the halt-machine event.
+ * Initialized in: linux
*
* CPU_BOOT_DEV_STS0_ENABLED Device status register enabled.
* This is a main indication that the
@@ -130,7 +137,7 @@
* register. Meaning the device status
* bits are not garbage, but actual
* statuses.
- * Initialized at: preboot
+ * Initialized in: preboot
*/
#define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << 0)
#define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << 1)
@@ -142,6 +149,7 @@
#define CPU_BOOT_DEV_STS0_RL_EN (1 << 7)
#define CPU_BOOT_DEV_STS0_SRAM_SCR_EN (1 << 8)
#define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << 9)
+#define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << 10)
#define CPU_BOOT_DEV_STS0_ENABLED (1 << 31)
enum cpu_boot_status {