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authorJungseung Lee <js07.lee@samsung.com>2020-04-21 09:33:13 +0300
committerTudor Ambarus <tudor.ambarus@microchip.com>2020-04-29 09:03:12 +0300
commitf80ff13135cb44a9be96f695d19212ae952ee5f4 (patch)
treeaf5a1fe70acc1505ed8616f722c0c8402620bef4 /drivers/mtd/spi-nor/micron-st.c
parent9f09e37d154469eb989918940fba64d8b1f8c42c (diff)
downloadlinux-f80ff13135cb44a9be96f695d19212ae952ee5f4.tar.xz
mtd: spi-nor: micron-st: Enable locking for n25q00
n25q00 uses the 4 bit Block Protection scheme and supports Top/Bottom protection via the BP and TB bits of the Status Register. Enable locking for n25q00. Tested with cirrus controller. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor/micron-st.c')
-rw-r--r--drivers/mtd/spi-nor/micron-st.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 02c0b53f6097..3dca5b9af3b6 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -61,6 +61,8 @@ static const struct flash_info st_parts[] = {
SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6 |
NO_CHIP_ERASE) },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |