diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2020-10-05 18:31:26 +0300 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2020-11-09 09:26:16 +0300 |
| commit | 0e30f47232ab57c685258aa91adc3a3e67bd023e (patch) | |
| tree | 81fd5cdadd13f4a44625876a76517a75bf537655 /drivers/mtd/spi-nor/sfdp.c | |
| parent | 6e1bf55d7207aa360c8d1960dfac6af1940bd32e (diff) | |
| download | linux-0e30f47232ab57c685258aa91adc3a3e67bd023e.tar.xz | |
mtd: spi-nor: add support for DTR protocol
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All phases need to be either DTR or STR.
The xSPI spec says that "The program commands provide SPI backward
compatible commands for programming data...". So 8D-8D-8D page program
opcodes are populated with using 1S-1S-1S opcodes.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20201005153138.6437-4-p.yadav@ti.com
Diffstat (limited to 'drivers/mtd/spi-nor/sfdp.c')
| -rw-r--r-- | drivers/mtd/spi-nor/sfdp.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index e2a43d39eb5f..21fa9ab78eae 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -1047,9 +1047,16 @@ static int spi_nor_parse_4bait(struct spi_nor *nor, } /* 4BAIT is the only SFDP table that indicates page program support. */ - if (pp_hwcaps & SNOR_HWCAPS_PP) + if (pp_hwcaps & SNOR_HWCAPS_PP) { spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP], SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); + /* + * Since xSPI Page Program opcode is backward compatible with + * Legacy SPI, use Legacy SPI opcode there as well. + */ + spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_8_8_8_DTR], + SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); + } if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4) spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4], SPINOR_OP_PP_1_1_4_4B, |