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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2013-08-12 21:14:51 +0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2013-08-31 00:34:54 +0400
commit41a634303f8dbf97c8087773b9d66914d2a9c0fd (patch)
tree7a6ec9d0bc1091cc921724612780bd2aa11e695f /drivers/mtd
parent3a1a344a79de3391f4122975eab1167b641668b9 (diff)
downloadlinux-41a634303f8dbf97c8087773b9d66914d2a9c0fd.tar.xz
mtd: nand: pxa3xx: Use 'length override' in ONFI paramater page read
The ONFI command 'parameter page read' needs a non-standard length. Therefore, we enable the 'length override' field in NDCB0 and set a non-zero 'length count' in NDCB3. Additionally, the 'spare enable' bit must be disabled for any command that sets a non-zero 'length count' in NDCB3. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index b3fc146cdccf..beef5bcf84ec 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -80,6 +80,7 @@
#define NDSR_RDDREQ (0x1 << 1)
#define NDSR_WRCMDREQ (0x1)
+#define NDCB0_LEN_OVRD (0x1 << 28)
#define NDCB0_ST_ROW_EN (0x1 << 26)
#define NDCB0_AUTO_RS (0x1 << 25)
#define NDCB0_CSEL (0x1 << 24)
@@ -562,6 +563,9 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
case NAND_CMD_READOOB:
pxa3xx_set_datasize(info);
break;
+ case NAND_CMD_PARAM:
+ info->use_spare = 0;
+ break;
case NAND_CMD_SEQIN:
exec_cmd = 0;
break;
@@ -637,8 +641,10 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
info->buf_count = 256;
info->ndcb0 |= NDCB0_CMD_TYPE(0)
| NDCB0_ADDR_CYC(1)
+ | NDCB0_LEN_OVRD
| cmd;
info->ndcb1 = (column & 0xFF);
+ info->ndcb3 = 256;
info->data_size = 256;
break;