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authorAndrew Lunn <andrew@lunn.ch>2015-11-03 18:52:36 +0300
committerDavid S. Miller <davem@davemloft.net>2015-11-03 19:29:57 +0300
commit4c7ea3c0791e971f05f78453a587a1640fe09a61 (patch)
tree7e96e87603b70b8e72f9d2c69d88f80d2caa33d6 /drivers/net/dsa
parent5ba3f7d61a3a9e6d94462b207d302931b53d8c61 (diff)
downloadlinux-4c7ea3c0791e971f05f78453a587a1640fe09a61.tar.xz
net: dsa: mv88e6xxx: disable SA learning for DSA and CPU ports
Frames with DSA headers passing to/from the CPU were taking place in the MAC learning on these ports, resulting in incorrect ATU entries. Disable learning on these ports. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa')
-rw-r--r--drivers/net/dsa/mv88e6xxx.c8
-rw-r--r--drivers/net/dsa/mv88e6xxx.h5
2 files changed, 11 insertions, 2 deletions
diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c
index 85228f44c2b5..3116990ccab9 100644
--- a/drivers/net/dsa/mv88e6xxx.c
+++ b/drivers/net/dsa/mv88e6xxx.c
@@ -2029,8 +2029,12 @@ static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
* a port bitmap that has only the bit for this port set and
* the other bits clear.
*/
- ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
- 1 << port);
+ reg = 1 << port;
+ /* Disable learning for DSA and CPU ports */
+ if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
+ reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
+
+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
if (ret)
goto abort;
diff --git a/drivers/net/dsa/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx.h
index ad9958f09aa7..fb9a8739712f 100644
--- a/drivers/net/dsa/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx.h
@@ -159,6 +159,11 @@
#define PORT_RATE_CONTROL 0x09
#define PORT_RATE_CONTROL_2 0x0a
#define PORT_ASSOC_VECTOR 0x0b
+#define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15)
+#define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14)
+#define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13)
+#define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12)
+#define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11)
#define PORT_ATU_CONTROL 0x0c
#define PORT_PRI_OVERRIDE 0x0d
#define PORT_ETH_TYPE 0x0f