diff options
| author | Hao Lan <lanhao@huawei.com> | 2024-03-07 04:01:09 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2024-03-08 15:01:32 +0300 |
| commit | dd1f65f0db27467f742d8c6e5276b8e8e0c83890 (patch) | |
| tree | 70c0523f8b49a27f804d7545b08d4a83ebe7be3a /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | |
| parent | 07a1d6dc90baedcf5d713e2b003b9e387130ee30 (diff) | |
| download | linux-dd1f65f0db27467f742d8c6e5276b8e8e0c83890.tar.xz | |
net: hns3: add new 200G link modes for hisilicon device
The hisilicon device now supports a new 200G link interface,
which query from firmware in a new bit. Therefore,
the HCLGE_SUPPORT_200G_R4_BIT capability bit has been added.
The HCLGE_SUPPORT_200G_BIT has been renamed as
HCLGE_SUPPORT_200G_R4_EXT_BIT, and the firmware has
extended support for this mode.
Fixes: ae6f010cb1a7 ("net: hns3: add support for 200G device")
Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index 51979cf71262..a2877b64e085 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -191,9 +191,10 @@ enum HLCGE_PORT_TYPE { #define HCLGE_SUPPORT_40G_BIT BIT(5) #define HCLGE_SUPPORT_100M_BIT BIT(6) #define HCLGE_SUPPORT_10M_BIT BIT(7) -#define HCLGE_SUPPORT_200G_BIT BIT(8) +#define HCLGE_SUPPORT_200G_R4_EXT_BIT BIT(8) #define HCLGE_SUPPORT_50G_R1_BIT BIT(9) #define HCLGE_SUPPORT_100G_R2_BIT BIT(10) +#define HCLGE_SUPPORT_200G_R4_BIT BIT(11) #define HCLGE_SUPPORT_GE \ (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) @@ -201,6 +202,8 @@ enum HLCGE_PORT_TYPE { (HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT) #define HCLGE_SUPPORT_100G_BITS \ (HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT) +#define HCLGE_SUPPORT_200G_BITS \ + (HCLGE_SUPPORT_200G_R4_EXT_BIT | HCLGE_SUPPORT_200G_R4_BIT) enum HCLGE_DEV_STATE { HCLGE_STATE_REINITING, |