diff options
| author | Veerasenareddy Burru <vburru@marvell.com> | 2023-03-24 20:46:58 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-03-27 10:37:54 +0300 |
| commit | 7c05d3d06c2382a2dee567b6ae5de4876a50de14 (patch) | |
| tree | 2120d84f37d15e6999d3fd75779fd8d8f3fd93b3 /drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c | |
| parent | 24d4333233b378114106a1327d3d635a004f4387 (diff) | |
| download | linux-7c05d3d06c2382a2dee567b6ae5de4876a50de14.tar.xz | |
octeon_ep: control mailbox for multiple PFs
Add control mailbox support for multiple PFs.
Update control mbox base address calculation based on PF function link.
Signed-off-by: Veerasenareddy Burru <vburru@marvell.com>
Signed-off-by: Abhijit Ayarekar <aayarekar@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index adc2279bc66d..e2503c9bc8a1 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -13,6 +13,9 @@ #include "octep_main.h" #include "octep_regs_cn9k_pf.h" +#define CTRL_MBOX_MAX_PF 128 +#define CTRL_MBOX_SZ ((size_t)(0x400000 / CTRL_MBOX_MAX_PF)) + /* Names of Hardware non-queue generic interrupts */ static char *cn93_non_ioq_msix_names[] = { "epf_ire_rint", @@ -198,7 +201,9 @@ static void octep_init_config_cn93_pf(struct octep_device *oct) { struct octep_config *conf = oct->conf; struct pci_dev *pdev = oct->pdev; + u8 link = 0; u64 val; + int pos; /* Read ring configuration: * PF ring count, number of VFs and rings per VF supported @@ -234,7 +239,16 @@ static void octep_init_config_cn93_pf(struct octep_device *oct) conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings; conf->msix_cfg.non_ioq_msix_names = cn93_non_ioq_msix_names; - conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + (0x400000ull * 7); + pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV); + if (pos) { + pci_read_config_byte(oct->pdev, + pos + PCI_SRIOV_FUNC_LINK, + &link); + link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link); + } + conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + + (0x400000ull * 7) + + (link * CTRL_MBOX_SZ); } /* Setup registers for a hardware Tx Queue */ |