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authorSunil Goutham <sgoutham@marvell.com>2019-11-14 08:26:29 +0300
committerDavid S. Miller <davem@davemloft.net>2019-11-15 05:09:16 +0300
commit5d9b976d4480dc0dcfa3719b645636d2f0f9f156 (patch)
tree1d38379c77e0f09aa22723f4a7fea767d56badc6 /drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
parent206ff848a1abaa1755310fdb4b20a3303ccf23d9 (diff)
downloadlinux-5d9b976d4480dc0dcfa3719b645636d2f0f9f156.tar.xz
octeontx2-af: Support fixed transmit scheduler topology
CN96xx initial silicon doesn't support all features pertaining to NIX transmit scheduling and shaping. - It supports a fixed topology of 1:1 mapped transmit limiters at all levels. - Supports DWRR only at SMQ/MDQ and TL1. - Doesn't support shaping and coloring. This patch adds HW capability structure by which each variant and skew of silicon can be differentiated by their supported features. And adds support for A0 silicon's transmit scheduler capabilities or rather limitations. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h')
-rw-r--r--drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
index 3d7b293c9e1d..be758c19648d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
@@ -246,6 +246,7 @@
#define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3)
#define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16)
+#define NIX_AF_SQM_DBG_CTL_STATUS (0x750)
#define NIX_AF_PSE_CHANNEL_LEVEL (0x800)
#define NIX_AF_PSE_SHAPER_CFG (0x810)
#define NIX_AF_TX_EXPR_CREDIT (0x830)