diff options
| author | Sunil Goutham <sgoutham@marvell.com> | 2018-10-22 20:56:01 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-10-23 06:15:38 +0300 |
| commit | 41a7aa7b800dd0a12d3bedc1947451e503dfee74 (patch) | |
| tree | 3d8b446d7c0fbae2d06a5eecd46cf7dbf2808bc2 /drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h | |
| parent | 759001406654f4ec8738a1149ed2729306bd335d (diff) | |
| download | linux-41a7aa7b800dd0a12d3bedc1947451e503dfee74.tar.xz | |
octeontx2-af: NIX Rx flowkey configuration for RSS
Configure NIX RX flowkey algorithm configuration to support
RSS (receive side scaling). Currently support for only L3/L4
2-tuple and 4-tuple hash of IPv4/v6/TCP/UDP/SCTP is added.
HW supports upto 32 different flowkey algorithms which SW
can define, this patch defines 9. NPC RX ACTION has to point
to one of these flowkey indices for RSS to work.
The configuration is dependent on NPC parse result's layer
info. So if NPC KPU profile changes suchthat LID/LTYPE values
of above said protocols change then this configuration will
most likely be effected.
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h index bb2836e18dd0..f920dac74e6c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h @@ -879,6 +879,36 @@ struct nix_lso_format { #endif }; +struct nix_rx_flowkey_alg { +#if defined(__BIG_ENDIAN_BITFIELD) + u64 reserved_35_63 :29; + u64 ltype_match :4; + u64 ltype_mask :4; + u64 sel_chan :1; + u64 ena :1; + u64 reserved_24_24 :1; + u64 lid :3; + u64 bytesm1 :5; + u64 hdr_offset :8; + u64 fn_mask :1; + u64 ln_mask :1; + u64 key_offset :6; +#else + u64 key_offset :6; + u64 ln_mask :1; + u64 fn_mask :1; + u64 hdr_offset :8; + u64 bytesm1 :5; + u64 lid :3; + u64 reserved_24_24 :1; + u64 ena :1; + u64 sel_chan :1; + u64 ltype_mask :4; + u64 ltype_match :4; + u64 reserved_35_63 :29; +#endif +}; + /* NIX VTAG size */ enum nix_vtag_size { VTAGSIZE_T4 = 0x0, |