diff options
| author | Leon Romanovsky <leonro@nvidia.com> | 2023-03-30 11:02:24 +0300 |
|---|---|---|
| committer | Leon Romanovsky <leonro@nvidia.com> | 2023-04-03 09:29:47 +0300 |
| commit | d05971a413d3c3dd207c604a6dbfc702070da63e (patch) | |
| tree | d1cc18ca84f7c4206ad7beadf32fe54e863df1b6 /drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h | |
| parent | 2da961d21663a72610f36a4f69b1090f2c61f23f (diff) | |
| download | linux-d05971a413d3c3dd207c604a6dbfc702070da63e.tar.xz | |
net/mlx5e: Add SW implementation to support IPsec 64 bit soft and hard limits
The CX7 cards which support IPsec packet offload use 32 bits to
configure soft and hard packet limits. This is not enough as the
software part using 64 bits.
The needed functionality of supporting 64 bits is implemented through
mlx5 abstraction layer, which will ensure that HW is reconfigured
on-demand every 2^31 packets.
To simulate the 64 bit IPsec soft/hard limits, we divide the soft/hard
limits to multiple interrupts (rounds). Each round counts 2^31 packets.
Once the counter is less than or equal to 2^31, the soft event is raised
and software sets the bit 31 of the counter and decrement the round
counter.
Link: https://lore.kernel.org/r/5a86c890b6dccb6865acf9042a8b03f899d1f3f9.1680162300.git.leonro@nvidia.com
Reviewed-by: Raed Salem <raeds@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index 68ae5230eb75..0c58c3583b0f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -60,6 +60,13 @@ struct upspec { u8 proto; }; +struct mlx5_ipsec_lft { + u64 hard_packet_limit; + u64 soft_packet_limit; + u64 numb_rounds_hard; + u64 numb_rounds_soft; +}; + struct mlx5_accel_esp_xfrm_attrs { u32 esn; u32 spi; @@ -85,8 +92,7 @@ struct mlx5_accel_esp_xfrm_attrs { u32 replay_window; u32 authsize; u32 reqid; - u64 hard_packet_limit; - u64 soft_packet_limit; + struct mlx5_ipsec_lft lft; }; enum mlx5_ipsec_cap { @@ -170,6 +176,12 @@ struct mlx5e_ipsec_modify_state_work { struct mlx5_accel_esp_xfrm_attrs attrs; }; +struct mlx5e_ipsec_limits { + u64 round; + u8 soft_limit_hit : 1; + u8 fix_limit : 1; +}; + struct mlx5e_ipsec_sa_entry { struct mlx5e_ipsec_esn_state esn_state; struct xfrm_state *x; @@ -181,6 +193,7 @@ struct mlx5e_ipsec_sa_entry { u32 enc_key_id; struct mlx5e_ipsec_rule ipsec_rule; struct mlx5e_ipsec_modify_state_work modify_work; + struct mlx5e_ipsec_limits limits; }; struct mlx5_accel_pol_xfrm_attrs { |