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| author | Maxim Mikityanskiy <maximmi@nvidia.com> | 2021-04-09 19:01:51 +0300 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2021-08-03 05:26:24 +0300 |
| commit | 43ec0f41fa73cc4d4f8a67e56fb398eff6881841 (patch) | |
| tree | d97a0e7c8271d17f3bedf2493c7210c8c9ceea81 /drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c | |
| parent | e6e01b5fdc281ea5819b21c48c813bcb156d3735 (diff) | |
| download | linux-43ec0f41fa73cc4d4f8a67e56fb398eff6881841.tar.xz | |
net/mlx5e: Hide all implementation details of mlx5e_rx_res
This commit moves all implementation details of struct mlx5e_rx_res
under en/rx_res.c. All access to RX resources is now done using methods.
Encapsulating RX resources into an object allows for better
manageability, because all the implementation details are now in a
single place, and external code can use only a limited set of API
methods to init/teardown the whole thing, reconfigure RSS and LRO
parameters, connect TIRs to flow steering and activate/deactivate TIRs.
mlx5e_rx_res is self-contained and doesn't depend on struct mlx5e_priv
or include en.h.
Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c | 19 |
1 files changed, 7 insertions, 12 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c index 494f6f832407..c057f830a15d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c @@ -433,9 +433,9 @@ add_ethtool_flow_rule(struct mlx5e_priv *priv, dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; if (group == MLX5E_RQ_GROUP_XSK) - dst->tir_num = priv->rx_res->channels[ix].xsk_tir.tirn; + dst->tir_num = mlx5e_rx_res_get_tirn_xsk(priv->rx_res, ix); else - dst->tir_num = priv->rx_res->channels[ix].direct_tir.tirn; + dst->tir_num = mlx5e_rx_res_get_tirn_direct(priv->rx_res, ix); flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; } @@ -819,6 +819,7 @@ static int mlx5e_set_rss_hash_opt(struct mlx5e_priv *priv, { enum mlx5e_traffic_types tt; u8 rx_hash_field = 0; + int err; tt = flow_type_to_traffic_type(nfc->flow_type); if (tt == MLX5E_NUM_INDIR_TIRS) @@ -848,16 +849,10 @@ static int mlx5e_set_rss_hash_opt(struct mlx5e_priv *priv, rx_hash_field |= MLX5_HASH_FIELD_SEL_L4_DPORT; mutex_lock(&priv->state_lock); - - if (rx_hash_field == priv->rx_res->rss_params.rx_hash_fields[tt]) - goto out; - - priv->rx_res->rss_params.rx_hash_fields[tt] = rx_hash_field; - mlx5e_modify_tirs_hash(priv); - -out: + err = mlx5e_rx_res_rss_set_hash_fields(priv->rx_res, tt, rx_hash_field); mutex_unlock(&priv->state_lock); - return 0; + + return err; } static int mlx5e_get_rss_hash_opt(struct mlx5e_priv *priv, @@ -870,7 +865,7 @@ static int mlx5e_get_rss_hash_opt(struct mlx5e_priv *priv, if (tt == MLX5E_NUM_INDIR_TIRS) return -EINVAL; - hash_field = priv->rx_res->rss_params.rx_hash_fields[tt]; + hash_field = mlx5e_rx_res_rss_get_hash_fields(priv->rx_res, tt); nfc->data = 0; if (hash_field & MLX5_HASH_FIELD_SEL_SRC_IP) |