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authorPrabhakar Kushwaha <pkushwaha@marvell.com>2021-10-04 09:58:47 +0300
committerDavid S. Miller <davem@davemloft.net>2021-10-04 14:55:49 +0300
commite2dbc2237692dbf297e2f2886a201ee44c30ae81 (patch)
tree56778e33abafd57c025e1336f2f2fa7472f63437 /drivers/net/ethernet/qlogic/qed/qed_rdma.c
parentb90cb5385af78d5bc9f439c0d0d7e188202c39b9 (diff)
downloadlinux-e2dbc2237692dbf297e2f2886a201ee44c30ae81.tar.xz
qed: Add '_GTT' suffix to the IRO RAM macros
GTT (Global translation table) is a fast-access window in the BAR into the register space, which only maps certain register addresses. This change helps enforce that only those addresses which are indeed mapped by the GTT are being accessed through it. Adding the '_GTT' suffix to the IRO FW memory (“RAM”) macros that access GTT-able region in FW memories (“RAM”) and use GTT macros to access RAM BAR from drivers. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qed/qed_rdma.c')
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_rdma.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_rdma.c b/drivers/net/ethernet/qlogic/qed/qed_rdma.c
index 05658e66a20b..fe0bb11d0e43 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_rdma.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_rdma.c
@@ -865,8 +865,8 @@ static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
}
qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
- addr = GTT_BAR0_MAP_REG_USDM_RAM +
- USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
+ addr = GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM,
+ USTORM_COMMON_QUEUE_CONS, qz_num);
REG_WR16(p_hwfn, addr, prod);