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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2019-02-04 21:05:55 +0300
committerDavid S. Miller <davem@davemloft.net>2019-02-05 00:31:00 +0300
commit2c2ab5af7d1470d7ba56525cc0c3eebe5ee2bad0 (patch)
tree26040c27b1a81a716fd3510e96a2b665ad50fc0d /drivers/net/ethernet/renesas/sh_eth.h
parentcc7335786f7278d66bdcf96d3d411edfcb01be51 (diff)
downloadlinux-2c2ab5af7d1470d7ba56525cc0c3eebe5ee2bad0.tar.xz
sh_eth: rename sh_eth_cpu_data::hw_checksum
Commit 62e04b7e0e3c ("sh_eth: rename 'sh_eth_cpu_data::hw_crc'") renamed the field to 'hw_checksum' for the Ether DMAC "intelligent checksum", however some Ether MACs implement a simpler checksumming scheme, so that name now seems misleading. Rename that field to 'csmr' as the "intelligent checksum" is always controlled by the CSMR register. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/renesas/sh_eth.h')
-rw-r--r--drivers/net/ethernet/renesas/sh_eth.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index 0c18650bbfe6..46d2fdf9d456 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -499,7 +499,7 @@ struct sh_eth_cpu_data {
unsigned no_ade:1; /* E-DMAC DOES NOT have ADE bit in EESR */
unsigned no_xdfar:1; /* E-DMAC DOES NOT have RDFAR/TDFAR */
unsigned xdfar_rw:1; /* E-DMAC has writeable RDFAR/TDFAR */
- unsigned hw_checksum:1; /* E-DMAC has CSMR */
+ unsigned csmr:1; /* E-DMAC has CSMR */
unsigned select_mii:1; /* EtherC has RMII_MII (MII select register) */
unsigned rmiimode:1; /* EtherC has RMIIMODE register */
unsigned rtrate:1; /* EtherC has RTRATE register */