diff options
author | Robert Richter <rrichter@amd.com> | 2024-02-16 19:01:13 +0300 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2024-02-17 10:20:34 +0300 |
commit | 0cab687205986491302cd2e440ef1d253031c221 (patch) | |
tree | 0117d9c9ef7e39a17724a36491527828e72a8a59 /drivers/net/ethernet | |
parent | 117132edc6900621337b77d29e953d0d01f32a5f (diff) | |
download | linux-0cab687205986491302cd2e440ef1d253031c221.tar.xz |
cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window
The Linux CXL subsystem is built on the assumption that HPA == SPA.
That is, the host physical address (HPA) the HDM decoder registers are
programmed with are system physical addresses (SPA).
During HDM decoder setup, the DVSEC CXL range registers (cxl-3.1,
8.1.3.8) are checked if the memory is enabled and the CXL range is in
a HPA window that is described in a CFMWS structure of the CXL host
bridge (cxl-3.1, 9.18.1.3).
Now, if the HPA is not an SPA, the CXL range does not match a CFMWS
window and the CXL memory range will be disabled then. The HDM decoder
stops working which causes system memory being disabled and further a
system hang during HDM decoder initialization, typically when a CXL
enabled kernel boots.
Prevent a system hang and do not disable the HDM decoder if the
decoder's CXL range is not found in a CFMWS window.
Note the change only fixes a hardware hang, but does not implement
HPA/SPA translation. Support for this can be added in a follow on
patch series.
Signed-off-by: Robert Richter <rrichter@amd.com>
Fixes: 34e37b4c432c ("cxl/port: Enable HDM Capability after validating DVSEC Ranges")
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20240216160113.407141-1-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/net/ethernet')
0 files changed, 0 insertions, 0 deletions