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authorAlex Elder <elder@linaro.org>2020-12-01 02:37:10 +0300
committerJakub Kicinski <kuba@kernel.org>2020-12-02 05:05:28 +0300
commit36426411021a6b4082c6203a6e9ee244c5887026 (patch)
treebf5a486487915d9be718098eb4683787fba052dc /drivers/net/ipa/ipa_reg.h
parent6bf754c7e677a0fbd8915316e4a944a0aded9af1 (diff)
downloadlinux-36426411021a6b4082c6203a6e9ee244c5887026.tar.xz
net: ipa: set up IPA v4.5 Qtime configuration
IPA v4.5 introduces a new unified timer architecture driven on the 19.2 MHz SoC crystal oscillator (XO). It is independent of the IPA core clock and avoids some duplication. Lower-resolution time stamps are derived from this by using only the high-order bits of the 19.2 MHz Qtime clock. And timers are derived from this based on "pulse generators" configured to fire at a fixed rate based on the Qtime clock. This patch introduces ipa_qtime_config(), which configures the Qtime mechanism for use. It also adds to the IPA register definitions related to timers and time stamping. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ipa/ipa_reg.h')
-rw-r--r--drivers/net/ipa/ipa_reg.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h
index 09dcfa2998f0..e6b0827a244e 100644
--- a/drivers/net/ipa/ipa_reg.h
+++ b/drivers/net/ipa/ipa_reg.h
@@ -223,6 +223,7 @@ static inline u32 ipa_reg_bcr_val(enum ipa_version version)
/* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */
#define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec
+/* The next register is not present for IPA v4.5 */
#define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0
#define AGGR_GRANULARITY_FMASK GENMASK(8, 4)
@@ -274,6 +275,35 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version)
#define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0)
#define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16)
+/* The next register is present for IPA v4.5 */
+#define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c
+#define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0)
+#define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7)
+#define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8)
+#define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16)
+
+/* The next register is present for IPA v4.5 */
+#define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250
+#define DIV_VALUE_FMASK GENMASK(8, 0)
+#define DIV_ENABLE_FMASK GENMASK(31, 31)
+
+/* The next register is present for IPA v4.5 */
+#define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254
+#define GRAN_0_FMASK GENMASK(2, 0)
+#define GRAN_1_FMASK GENMASK(5, 3)
+#define GRAN_2_FMASK GENMASK(8, 6)
+/* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */
+enum ipa_pulse_gran {
+ IPA_GRAN_10_US = 0x0,
+ IPA_GRAN_20_US = 0x1,
+ IPA_GRAN_50_US = 0x2,
+ IPA_GRAN_100_US = 0x3,
+ IPA_GRAN_1_MS = 0x4,
+ IPA_GRAN_10_MS = 0x5,
+ IPA_GRAN_100_MS = 0x6,
+ IPA_GRAN_655350_US = 0x7,
+};
+
/* # IPA source resource groups available based on version */
static inline u32 ipa_resource_group_src_count(enum ipa_version version)
{