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authorJakub Kicinski <kuba@kernel.org>2023-07-28 01:21:46 +0300
committerJakub Kicinski <kuba@kernel.org>2023-07-28 01:22:46 +0300
commit014acf26685cfcfae37c9e98b83c622c0b01cf19 (patch)
tree85ce0217698aef25875fdc62f2332bbbbc1bff2c /drivers/net/phy
parent9d0cd5d25f7d45bce01bbb3193b54ac24b3a60f3 (diff)
parent57012c57536f8814dec92e74197ee96c3498d24e (diff)
downloadlinux-014acf26685cfcfae37c9e98b83c622c0b01cf19.tar.xz
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Cross-merge networking fixes after downstream PR. No conflicts or adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/phy')
-rw-r--r--drivers/net/phy/marvell10g.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 55d9d7acc32e..d4bb90d76881 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev)
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
MV_V2_PORT_CTRL_PWRDOWN);
+ /* Sometimes, the power down bit doesn't clear immediately, and
+ * a read of this register causes the bit not to clear. Delay
+ * 100us to allow the PHY to come out of power down mode before
+ * the next access.
+ */
+ udelay(100);
+
if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
priv->firmware_ver < 0x00030000)
return ret;