diff options
| author | Sara Sharon <sara.sharon@intel.com> | 2016-04-17 16:28:18 +0300 |
|---|---|---|
| committer | Luca Coelho <luciano.coelho@intel.com> | 2016-07-01 18:09:42 +0300 |
| commit | 1316d5957be3b311b1494382172d4acb2f36ea59 (patch) | |
| tree | 8827623827138eab433a30c0432f9ae77bb4cbba /drivers/net/wireless/intel/iwlwifi/iwl-csr.h | |
| parent | a6f035a008366a03378ed27560794d84a237895b (diff) | |
| download | linux-1316d5957be3b311b1494382172d4acb2f36ea59.tar.xz | |
iwlwifi: pcie: workaround HW shadow registers bug
Integrated 9000 devices have a bug with shadow registers
value retention.
If driver writes RBD registers while MAC is asleep the
values are stored in shadow registers to be copied whenever
MAC wakes up.
However, in 9000 devices a MAC wakeup is not triggered
and when the bus powers down due to inactivity the shadow
values and dirty bits are lost.
Turn on the chicken-bits that cause MAC wakeup for RX-related
values as well when the device is in D0.
When the device is in low power mode turn the RX wakeup chicken
bits off since driver is idle and this W/A is not needed.
Remove previous W/A which was ineffective.
Signed-off-by: Sara Sharon <sara.sharon@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Diffstat (limited to 'drivers/net/wireless/intel/iwlwifi/iwl-csr.h')
| -rw-r--r-- | drivers/net/wireless/intel/iwlwifi/iwl-csr.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h index b52913448c4a..871ad02fdb17 100644 --- a/drivers/net/wireless/intel/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-csr.h @@ -145,8 +145,10 @@ #define CSR_LED_REG (CSR_BASE+0x094) #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) -#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */ - +#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */ +#define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20) +#define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC) +#define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF /* GIO Chicken Bits (PCI Express bus link power management) */ #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |