diff options
author | Zong-Zhe Yang <kevin_yang@realtek.com> | 2023-10-03 04:54:44 +0300 |
---|---|---|
committer | Kalle Valo <kvalo@kernel.org> | 2023-10-05 09:54:16 +0300 |
commit | 932f85c18aef095dc8b573112f6c3b955ff43a72 (patch) | |
tree | d0b80ff3f6c1580a8d3ffa15ed9dd91384e3fb6e /drivers/net/wireless/realtek/rtw89/phy.c | |
parent | 70aa04f2d58cc5f3a94ce02f6442e9bac6c2468e (diff) | |
download | linux-932f85c18aef095dc8b573112f6c3b955ff43a72.tar.xz |
wifi: rtw89: phy: set TX power RU limit according to chip gen
Wi-Fi 6 chips and Wi-Fi 7 chips have different register design for TX
power RU limit. We rename original setting stuffs with a suffix `_ax`,
concentrate related enum declaration in phy.h, and implement setting
flow for Wi-Fi 7 chips. Then, we set TX power RU limit according to
chip generation.
Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231003015446.14658-6-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/phy.c')
-rw-r--r-- | drivers/net/wireless/realtek/rtw89/phy.c | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index ab132f9aef7d..d04eaf7c5500 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -1906,8 +1906,8 @@ void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, } } -static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, - u8 ru, u8 ntx, u8 ch) +s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, + u8 ru, u8 ntx, u8 ch) { const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; @@ -1957,9 +1957,9 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, } static void -rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, - struct rtw89_txpwr_limit_ru *lmt_ru, - u8 band, u8 ntx, u8 ch) +rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, + struct rtw89_txpwr_limit_ru_ax *lmt_ru, + u8 band, u8 ntx, u8 ch) { lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU26, @@ -1973,9 +1973,9 @@ rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, } static void -rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, - struct rtw89_txpwr_limit_ru *lmt_ru, - u8 band, u8 ntx, u8 ch) +rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, + struct rtw89_txpwr_limit_ru_ax *lmt_ru, + u8 band, u8 ntx, u8 ch) { lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU26, @@ -1998,9 +1998,9 @@ rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, } static void -rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, - struct rtw89_txpwr_limit_ru *lmt_ru, - u8 band, u8 ntx, u8 ch) +rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, + struct rtw89_txpwr_limit_ru_ax *lmt_ru, + u8 band, u8 ntx, u8 ch) { lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU26, @@ -2041,15 +2041,15 @@ rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, } static void -rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, - struct rtw89_txpwr_limit_ru *lmt_ru, - u8 band, u8 ntx, u8 ch) +rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, + struct rtw89_txpwr_limit_ru_ax *lmt_ru, + u8 band, u8 ntx, u8 ch) { static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; int i; - static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); - for (i = 0; i < RTW89_RU_SEC_NUM; i++) { + static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); + for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, RTW89_RU26, ntx, @@ -2066,10 +2066,10 @@ rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, } static -void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, - const struct rtw89_chan *chan, - struct rtw89_txpwr_limit_ru *lmt_ru, - u8 ntx) +void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, + const struct rtw89_chan *chan, + struct rtw89_txpwr_limit_ru_ax *lmt_ru, + u8 ntx) { u8 band = chan->band_type; u8 ch = chan->channel; @@ -2079,20 +2079,20 @@ void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, switch (bw) { case RTW89_CHANNEL_WIDTH_20: - rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, - ch); + rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, + ch); break; case RTW89_CHANNEL_WIDTH_40: - rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, - ch); + rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, + ch); break; case RTW89_CHANNEL_WIDTH_80: - rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, - ch); + rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, + ch); break; case RTW89_CHANNEL_WIDTH_160: - rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, - ch); + rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, + ch); break; } } @@ -2217,12 +2217,12 @@ static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, } } -void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, - const struct rtw89_chan *chan, - enum rtw89_phy_idx phy_idx) +static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, + const struct rtw89_chan *chan, + enum rtw89_phy_idx phy_idx) { u8 max_ntx_num = rtwdev->chip->rf_path_num; - struct rtw89_txpwr_limit_ru lmt_ru; + struct rtw89_txpwr_limit_ru_ax lmt_ru; u8 ch = chan->channel; u8 bw = chan->band_width; const s8 *ptr; @@ -2232,15 +2232,15 @@ void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); - BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) != - RTW89_TXPWR_LMT_RU_PAGE_SIZE); + BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != + RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); addr = R_AX_PWR_RU_LMT; for (i = 0; i < max_ntx_num; i++) { - rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i); + rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); ptr = (s8 *)&lmt_ru; - for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE; + for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; j += 4, addr += 4, ptr += 4) { val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | FIELD_PREP(GENMASK(15, 8), ptr[1]) | @@ -2251,7 +2251,6 @@ void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, } } } -EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru); struct rtw89_phy_iter_ra_data { struct rtw89_dev *rtwdev; @@ -4906,5 +4905,6 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, + .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, }; EXPORT_SYMBOL(rtw89_phy_gen_ax); |