diff options
| author | Ping-Ke Shih <pkshih@realtek.com> | 2024-01-05 09:44:22 +0300 |
|---|---|---|
| committer | Kalle Valo <kvalo@kernel.org> | 2024-01-10 17:50:57 +0300 |
| commit | c207e14d9328a97635dd78090e4296ef97149a2d (patch) | |
| tree | ad6a595b8e0ce9c81c867e0c81f0d579eb1da292 /drivers/net/wireless/realtek/rtw89/reg.h | |
| parent | 0377e2a77201f22bb7336b5671f3f43fc094b44a (diff) | |
| download | linux-c207e14d9328a97635dd78090e4296ef97149a2d.tar.xz | |
wifi: rtw89: 8922a: add NCTL pre-settings for WiFi 7 chips
NCTL standing for nano-controller is used to assist RF calibration.
Basically, we write settings from a table, but format of the table can't
describe register mask and additional conditions, so add a function to
set this kind of settings.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://msgid.link/20240105064422.36812-1-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/reg.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/reg.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 61ba52d5990e..dc237f12dc5e 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -7588,13 +7588,20 @@ #define R_PD_CTRL 0x0C3C #define B_PD_HIT_DIS BIT(9) #define R_IOQ_IQK_DPK 0x0C60 +#define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0) #define B_IOQ_IQK_DPK_EN BIT(1) #define R_GNT_BT_WGT_EN 0x0C6C #define B_GNT_BT_WGT_EN BIT(21) +#define R_IQK_DPK_RST 0x0C6C +#define R_IQK_DPK_RST_C1 0x1C6C +#define B_IQK_DPK_RST BIT(0) #define R_TX_COLLISION_T2R_ST 0x0C70 #define B_TX_COLLISION_T2R_ST_M GENMASK(25, 20) #define R_TXGATING 0x0C74 #define B_TXGATING_EN BIT(4) +#define R_TXRFC 0x0C7C +#define R_TXRFC_C1 0x1C7C +#define B_TXRFC_RST GENMASK(23, 21) #define R_PD_ARBITER_OFF 0x0C80 #define B_PD_ARBITER_OFF BIT(31) #define R_SNDCCA_A1 0x0C9C @@ -7624,6 +7631,8 @@ #define R_CTLTOP 0x1008 #define B_CTLTOP_ON BIT(23) #define B_CTLTOP_VAL GENMASK(15, 12) +#define R_CLK_GCK 0x1008 +#define B_CLK_GCK GENMASK(24, 0) #define R_EDCCA_RPT_SEL_BE 0x10CC #define R_S0_HW_SI_DIS 0x1200 #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) @@ -7771,6 +7780,8 @@ #define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13) #define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10 #define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0) +#define R_IQKDPK_HC 0x2AB8 +#define B_IQKDPK_HC BIT(28) #define R_P1_EN_SOUND_WO_NDP 0x2D7C #define B_P1_EN_SOUND_WO_NDP BIT(1) #define R_EDCCA_RPT_A_BE 0x2E38 @@ -8630,6 +8641,12 @@ #define B_DACKN0_V GENMASK(21, 14) #define R_DACKN1_CTL 0xC224 #define B_DACKN1_V GENMASK(21, 14) +#define R_GOTX_IQKDPK_C0 0xE464 +#define R_GOTX_IQKDPK_C1 0xE564 +#define B_GOTX_IQKDPK GENMASK(28, 27) +#define R_IQK_DPK_PRST 0xE4AC +#define R_IQK_DPK_PRST_C1 0xE5AC +#define B_IQK_DPK_PRST BIT(27) /* WiFi CPU local domain */ #define R_AX_WDT_CTRL 0x0040 |