diff options
| author | Ping-Ke Shih <pkshih@realtek.com> | 2023-11-10 04:23:17 +0300 |
|---|---|---|
| committer | Kalle Valo <kvalo@kernel.org> | 2023-11-14 13:22:42 +0300 |
| commit | d8872fb60e720ed656e03883e9bed576a72e0006 (patch) | |
| tree | b0cf3144183f2ab8411e569162974c1c7bc57ff4 /drivers/net/wireless/realtek/rtw89/reg.h | |
| parent | aa70f76120ee4e67b1ba90a2e2ec1fea595cf108 (diff) | |
| download | linux-d8872fb60e720ed656e03883e9bed576a72e0006.tar.xz | |
wifi: rtw89: 8922ae: add v2 interrupt handlers for 8922AE
The handlers include three parts -- 1) configure interrupt mask;
2) enable/disable interrupt; 3) recognize (read) interrupt status.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231110012319.12727-6-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/reg.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/reg.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 51a0394eee3c..080db70b87d2 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -3826,6 +3826,33 @@ #define B_BE_FS_GPIO17_INT_EN BIT(1) #define B_BE_FS_GPIO16_INT_EN BIT(0) +#define R_BE_HIMR0 0x01A0 +#define B_BE_WDT_DATACPU_TIMEOUT_INT_EN BIT(25) +#define B_BE_HALT_D2H_INT_EN BIT(24) +#define B_BE_WDT_TIMEOUT_INT_EN BIT(22) +#define B_BE_HALT_C2H_INT_EN BIT(21) +#define B_BE_RON_INT_EN BIT(20) +#define B_BE_PDNINT_EN BIT(19) +#define B_BE_SPSANA_OCP_INT_EN BIT(18) +#define B_BE_SPS_OCP_INT_EN BIT(17) +#define B_BE_BTON_STS_UPDATE_INT_EN BIT(16) +#define B_BE_GPIOF_INT_EN BIT(15) +#define B_BE_GPIOE_INT_EN BIT(14) +#define B_BE_GPIOD_INT_EN BIT(13) +#define B_BE_GPIOC_INT_EN BIT(12) +#define B_BE_GPIOB_INT_EN BIT(11) +#define B_BE_GPIOA_INT_EN BIT(10) +#define B_BE_GPIO9_INT_EN BIT(9) +#define B_BE_GPIO8_INT_EN BIT(8) +#define B_BE_GPIO7_INT_EN BIT(7) +#define B_BE_GPIO6_INT_EN BIT(6) +#define B_BE_GPIO5_INT_EN BIT(5) +#define B_BE_GPIO4_INT_EN BIT(4) +#define B_BE_GPIO3_INT_EN BIT(3) +#define B_BE_GPIO2_INT_EN BIT(2) +#define B_BE_GPIO1_INT_EN BIT(1) +#define B_BE_GPIO0_INT_EN BIT(0) + #define R_BE_HISR0 0x01A4 #define B_BE_WDT_DATACPU_TIMEOUT_INT BIT(25) #define B_BE_HALT_D2H_INT BIT(24) |