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authorPing-Ke Shih <pkshih@realtek.com>2023-11-17 05:40:26 +0300
committerKalle Valo <kvalo@kernel.org>2023-11-22 18:51:16 +0300
commitf28eab6ae4ff016d01226364c9099d4eacffbb1a (patch)
tree91d514272778e2c1b645a276e5a21f4c945480e0 /drivers/net/wireless/realtek/rtw89/reg.h
parent88e6a923bbfbdd4fd2e92ff50902251884927dac (diff)
downloadlinux-f28eab6ae4ff016d01226364c9099d4eacffbb1a.tar.xz
wifi: rtw89: mac: add to access efuse for WiFi 7 chips
MAC address, hardware type, calibration values and etc are stored in efuse, so we read them at probe stage and use them as capabilities to register hardware. There are two physical efuse -- one is the main efuse for digital hardware part, and the other is for analog part. Because they are very similar, we only describe the main efuse below. The main efuse is split into two regions -- one is for logic map, and the other is for physical map. For both regions, we use the same method to read data, but need additional parser to get logic map. To allow reading operation, we need to convert power state to active, and turn to idle state after reading. For WiFi 7 chips, we introduce efuse blocks to define feature group easier, and these blocks are discontinue. For example, RF block is from 0x1_0000 ~ 0x1_0240, and the next block PCIE_SDIO is starting from 0x2_0000. Comparing to old one used by WiFi 6 chips, there is only single one logic map, it would be a little hard to add an new field to a group if we don't reserve a room in advance. The relationship between efuse, region and block is shown as below: (logical map) +------------+ +---------------+ +-----------------+ | main efuse | | region 1 | | block 0x1_0000~ | | (digital) | |(to logcal map)| +-----------------+ | | | | => +-----------------+ | | => | | | block 0x2_0000~ | | | | | +-----------------+ | | |---------------| : | | | region 2 | +------------+ +---------------+ +------------+ +-----------------+ | 2nd efuse | ======================> | block 0x7_0000~ | | (analog) | +-----------------+ +------------+ The parser converting from raw data to logic map is to decode block page, block page offset, and word_en bits. Each word_en bit indicates two following bytes as data of logic map, so total four word_en bits can represent eight bytes. Thus, block page offset is 8-byte alignment. The layout of a tuple is shown as below +--------+--------+--------+--------+--------+--------+ | fixed 3 byte header | | | | | | | | | | [19:17] block_page | | | ... | | [16:4] block_page_offset| | | | | [3:0] word_en | ^ | ^ | | +----|---+--------+--------+---|----+----|---+--------+ | | | +-------------------------+---------+ a word_en bit indicates two bytes as data For example, block_page = 0x3 block_page_offset = 0x80 (must 8-byte alignment) word_en = 0x6 (b'0110; 0 means data is presented) following 4 bytes = 34 56 78 90 Then, 0x3_0080 = 34 56 0x3_0086 = 78 90 A special block page is RTW89_EFUSE_BLOCK_ADIE (7) that uses different but similar format, because its real efuse size is smaller than main efuse. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20231117024029.113845-4-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/reg.h')
-rw-r--r--drivers/net/wireless/realtek/rtw89/reg.h72
1 files changed, 72 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 7698fd3922f3..7a9ae6cd86e5 100644
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -3630,6 +3630,23 @@
#define B_AX_GNT_BT_TX_SW_VAL BIT(1)
#define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
+#define R_BE_SYS_ISO_CTRL 0x0000
+#define B_BE_PWC_EV2EF_B BIT(15)
+#define B_BE_PWC_EV2EF_S BIT(14)
+#define B_BE_PA33V_EN BIT(13)
+#define B_BE_PA12V_EN BIT(12)
+#define B_BE_PAOOBS33V_EN BIT(11)
+#define B_BE_PAOOBS12V_EN BIT(10)
+#define B_BE_ISO_RFDIO BIT(9)
+#define B_BE_ISO_EB2CORE BIT(8)
+#define B_BE_ISO_DIOE BIT(7)
+#define B_BE_ISO_WLPON2PP BIT(6)
+#define B_BE_ISO_IP2MAC_WA02PP BIT(5)
+#define B_BE_ISO_PD2CORE BIT(4)
+#define B_BE_ISO_PA2PCIE BIT(3)
+#define B_BE_ISO_PAOOBS2PCIE BIT(1)
+#define B_BE_ISO_WD2PP BIT(0)
+
#define R_BE_SYS_PW_CTRL 0x0004
#define B_BE_SOP_ASWRM BIT(31)
#define B_BE_SOP_EASWR BIT(30)
@@ -3667,6 +3684,16 @@
#define B_BE_ANA_CLK_DIVISION_2 BIT(1)
#define B_BE_CNTD16V_EN BIT(0)
+#define R_BE_SYS_WL_EFUSE_CTRL 0x000A
+#define B_BE_OTP_B_PWC_RPT BIT(15)
+#define B_BE_OTP_S_PWC_RPT BIT(14)
+#define B_BE_OTP_ISO_RPT BIT(13)
+#define B_BE_OTP_BURST_RPT BIT(12)
+#define B_BE_OTP_AUTOLOAD_RPT BIT(11)
+#define B_BE_AUTOLOAD_DIS_A_DIE BIT(6)
+#define B_BE_AUTOLOAD_SUS BIT(5)
+#define B_BE_AUTOLOAD_DIS BIT(4)
+
#define R_BE_SYS_PAGE_CLK_GATED 0x000C
#define B_BE_USB_APHY_PC_DLP_OP BIT(27)
#define B_BE_PCIE_APHY_PC_DLP_OP BIT(26)
@@ -3696,6 +3723,38 @@
#define B_BE_DIS_CLK_REG1_GATE BIT(1)
#define B_BE_DIS_CLK_REG0_GATE BIT(0)
+#define R_BE_EFUSE_CTRL 0x0030
+#define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)
+#define B_BE_EF_RDY BIT(29)
+#define B_BE_EF_COMP_RESULT BIT(28)
+#define B_BE_EF_ADDR_MASK GENMASK(15, 0)
+
+#define R_BE_EFUSE_CTRL_1_V1 0x0034
+#define B_BE_EF_DATA_MASK GENMASK(31, 0)
+
+#define R_BE_WL_BT_PWR_CTRL 0x0068
+#define B_BE_ISO_BD2PP BIT(31)
+#define B_BE_LDOV12B_EN BIT(30)
+#define B_BE_CKEN_BT BIT(29)
+#define B_BE_FEN_BT BIT(28)
+#define B_BE_BTCPU_BOOTSEL BIT(27)
+#define B_BE_SPI_SPEEDUP BIT(26)
+#define B_BE_BT_LDO_MODE BIT(25)
+#define B_BE_ISO_BTPON2PP BIT(22)
+#define B_BE_BT_FUNC_EN BIT(18)
+#define B_BE_BT_HWPDN_SL BIT(17)
+#define B_BE_BT_DISN_EN BIT(16)
+#define B_BE_SDM_SRC_SEL BIT(12)
+#define B_BE_ISO_BA2PP BIT(11)
+#define B_BE_BT_AFE_LDO_EN BIT(10)
+#define B_BE_BT_AFE_PLL_EN BIT(9)
+#define B_BE_WLAN_32K_SEL BIT(6)
+#define B_BE_WL_DRV_EXIST_IDX BIT(5)
+#define B_BE_DOP_EHPAD BIT(4)
+#define B_BE_WL_FUNC_EN BIT(2)
+#define B_BE_WL_HWPDN_SL BIT(1)
+#define B_BE_WL_HWPDN_EN BIT(0)
+
#define R_BE_SYS_SDIO_CTRL 0x0070
#define B_BE_MCM_FLASH_EN BIT(28)
#define B_BE_PCIE_SEC_LOAD BIT(26)
@@ -3780,6 +3839,19 @@
#define B_BE_EF_DSB_EN BIT(11)
#define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0)
+#define R_BE_PMC_DBG_CTRL2 0x00CC
+#define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
+#define B_BE_DIS_IOWRAP_TIMEOUT BIT(16)
+#define B_BE_STOP_WL_PMC BIT(9)
+#define B_BE_STOP_SYM_PMC BIT(8)
+#define B_BE_SYM_REG_PCIE_WRMSK BIT(7)
+#define B_BE_BT_ACCESS_WL_PAGE0 BIT(6)
+#define B_BE_R_BE_RST_WLPMC BIT(5)
+#define B_BE_R_BE_RST_PD12N BIT(4)
+#define B_BE_SYSON_DIS_WLR_BE_WRMSK BIT(3)
+#define B_BE_SYSON_DIS_PMCR_BE_WRMSK BIT(2)
+#define B_BE_SYSON_R_BE_ARB_MASK GENMASK(1, 0)
+
#define R_BE_HALT_H2C_CTRL 0x0160
#define B_BE_HALT_H2C_TRIGGER BIT(0)