diff options
| author | Jakub Kicinski <kuba@kernel.org> | 2024-03-08 20:05:48 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2024-03-08 20:05:49 +0300 |
| commit | 75c2946db360e625f1447a37f47dbbb38b1dd478 (patch) | |
| tree | 4d0f79c7ebfecdf3fdd5c703c5fe4459f5510e44 /drivers/net/wireless/realtek | |
| parent | 19cfdc0d57696c92523da8eb26c0f3e092400bee (diff) | |
| parent | f654e228ed6b822e87e6e6ad8e889bedccae2e16 (diff) | |
| download | linux-75c2946db360e625f1447a37f47dbbb38b1dd478.tar.xz | |
Merge tag 'wireless-next-2024-03-08' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
Kalle Valo says:
====================
wireless-next patches for v6.9
The fourth "new features" pull request for v6.9 with changes both in
stack and in drivers. The theme in this pull request is to fix sparse
warnings but we still have some left in wireless subsystem. Otherwise
quite normal.
Major changes:
rtw89
* NL80211_EXT_FEATURE_SCAN_RANDOM_SN support
* NL80211_EXT_FEATURE_SET_SCAN_DWELL support
rtw88
* support for more rtw8811cu and rtw8821cu devices
mt76
* mt76x2u: add Netgear WNDA3100v3 USB
* mt7915: newer ADIE version support
* mt7925: radio temperature sensor support
* mt7996: remove GCMP IGTK offload
* tag 'wireless-next-2024-03-08' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next: (125 commits)
wifi: rtw89: wow: move release offload packet earlier for WoWLAN mode
wifi: rtw89: wow: set security engine options for 802.11ax chips only
wifi: rtw89: update suspend/resume for different generation
wifi: rtw89: wow: update config mac function with different generation
wifi: rtw89: update DMA function with different generation
wifi: rtw89: wow: update WoWLAN status register for different generation
wifi: rtw89: wow: update WoWLAN reason register for different chips
wifi: brcm80211: handle pmk_op allocation failure
wifi: rtw89: coex: Add coexistence policy to decrease WiFi packet CRC-ERR
wifi: rtw89: coex: When Bluetooth not available don't set power/gain
wifi: rtw89: coex: add return value to ensure H2C command is success or not
wifi: rtw89: coex: Reorder H2C command index to align with firmware
wifi: rtw89: coex: add BTC ctrl_info version 7 and related logic
wifi: rtw89: coex: add init_info H2C command format version 7
wifi: rtw89: 8922a: add coexistence helpers of SW grant
wifi: rtw89: mac: add coexistence helpers {cfg/get}_plt
wifi: cw1200: restore endian swapping
wifi: wlcore: sdio: Rate limit wl12xx_sdio_raw_{read,write}() failures warns
wifi: rtlwifi: Remove rtl_intf_ops.read_efuse_byte
wifi: rtw88: 8821c: Fix false alarm count
...
====================
Link: https://lore.kernel.org/r/20240308100429.B8EA2C433F1@smtp.kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/wireless/realtek')
31 files changed, 1536 insertions, 368 deletions
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index efddbe402f0d..4a49f8f9d80f 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -4919,11 +4919,11 @@ static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) int i; for (i = 0; i < ARRAY_SIZE(priv->vifs); i++) { + struct ieee80211_sta *sta; + if (!priv->vifs[i]) continue; - struct ieee80211_sta *sta; - rcu_read_lock(); sta = ieee80211_find_sta(priv->vifs[i], priv->vifs[i]->bss_conf.bssid); if (sta) diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c index d059cfe5a2a9..11709b6c83f1 100644 --- a/drivers/net/wireless/realtek/rtlwifi/pci.c +++ b/drivers/net/wireless/realtek/rtlwifi/pci.c @@ -2374,7 +2374,6 @@ EXPORT_SYMBOL(rtl_pci_resume); #endif /* CONFIG_PM_SLEEP */ const struct rtl_intf_ops rtl_pci_ops = { - .read_efuse_byte = read_efuse_byte, .adapter_start = rtl_pci_start, .adapter_stop = rtl_pci_stop, .check_buddy_priv = rtl_pci_check_buddy_priv, diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c index 743ac6871bf4..4ba42f6be3f2 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c @@ -1669,10 +1669,8 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) u8 cutvalue[2]; u16 chipvalue; - rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, - &cutvalue[1]); - rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, - &cutvalue[0]); + read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, &cutvalue[1]); + read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, &cutvalue[0]); chipvalue = (cutvalue[1] << 8) | cutvalue[0]; switch (chipvalue) { case 0xAA55: diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h index f388d13e2ba8..9fabf597cfd6 100644 --- a/drivers/net/wireless/realtek/rtlwifi/wifi.h +++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h @@ -2289,7 +2289,6 @@ struct rtl_hal_ops { struct rtl_intf_ops { /*com */ - void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); int (*adapter_start)(struct ieee80211_hw *hw); void (*adapter_stop)(struct ieee80211_hw *hw); bool (*check_buddy_priv)(struct ieee80211_hw *hw, diff --git a/drivers/net/wireless/realtek/rtw88/mac.c b/drivers/net/wireless/realtek/rtw88/mac.c index 298663b03580..0c1c1ff31085 100644 --- a/drivers/net/wireless/realtek/rtw88/mac.c +++ b/drivers/net/wireless/realtek/rtw88/mac.c @@ -309,6 +309,13 @@ static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; ret = rtw_pwr_seq_parser(rtwdev, pwr_seq); + if (pwr_on && rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { + if (chip->id == RTW_CHIP_TYPE_8822C || + chip->id == RTW_CHIP_TYPE_8822B || + chip->id == RTW_CHIP_TYPE_8821C) + rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0)); + } + if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) rtw_write32(rtwdev, REG_SDIO_HIMR, imr); diff --git a/drivers/net/wireless/realtek/rtw88/main.c b/drivers/net/wireless/realtek/rtw88/main.c index 6d22628129d0..ffba6b88f392 100644 --- a/drivers/net/wireless/realtek/rtw88/main.c +++ b/drivers/net/wireless/realtek/rtw88/main.c @@ -2032,8 +2032,6 @@ static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type); rtw_phy_init_tx_power(rtwdev); - if (rfe_def->agc_btg_tbl) - rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); rtw_phy_tx_power_by_rate_config(hal); diff --git a/drivers/net/wireless/realtek/rtw88/phy.c b/drivers/net/wireless/realtek/rtw88/phy.c index 128e75a81bf3..37ef80c9091d 100644 --- a/drivers/net/wireless/realtek/rtw88/phy.c +++ b/drivers/net/wireless/realtek/rtw88/phy.c @@ -1761,12 +1761,15 @@ static void rtw_load_rfk_table(struct rtw_dev *rtwdev) void rtw_phy_load_tables(struct rtw_dev *rtwdev) { + const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); const struct rtw_chip_info *chip = rtwdev->chip; u8 rf_path; rtw_load_table(rtwdev, chip->mac_tbl); rtw_load_table(rtwdev, chip->bb_tbl); rtw_load_table(rtwdev, chip->agc_tbl); + if (rfe_def->agc_btg_tbl) + rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); rtw_load_rfk_table(rtwdev); for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) { diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c.c b/drivers/net/wireless/realtek/rtw88/rtw8821c.c index 429bb420b056..fe5d8e188350 100644 --- a/drivers/net/wireless/realtek/rtw88/rtw8821c.c +++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.c @@ -773,9 +773,9 @@ static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev) dm_info->cck_fa_cnt = cck_fa_cnt; dm_info->ofdm_fa_cnt = ofdm_fa_cnt; + dm_info->total_fa_cnt = ofdm_fa_cnt; if (cck_enable) dm_info->total_fa_cnt += cck_fa_cnt; - dm_info->total_fa_cnt = ofdm_fa_cnt; crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821cu.c b/drivers/net/wireless/realtek/rtw88/rtw8821cu.c index 7a5cbdc31ef7..e2c7d9f87683 100644 --- a/drivers/net/wireless/realtek/rtw88/rtw8821cu.c +++ b/drivers/net/wireless/realtek/rtw88/rtw8821cu.c @@ -9,24 +9,36 @@ #include "usb.h" static const struct usb_device_id rtw_8821cu_id_table[] = { - { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xb82b, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8821CU */ + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0x2006, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0x8731, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0x8811, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xb820, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8821CU */ - { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc821, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8821CU */ + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xb82b, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc80c, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc811, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc820, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8821CU */ + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc821, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc82a, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8821CU */ + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc82b, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8821CU */ - { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc811, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8811CU */ - { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0x8811, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* 8811CU */ - { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0x2006, 0xff, 0xff, 0xff), - .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* TOTOLINK A650UA v3 */ + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(RTW_USB_VENDOR_ID_REALTEK, 0xc82c, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, + { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331d, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* D-Link */ + { USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xc811, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* Edimax */ + { USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xd811, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* Edimax */ {}, }; MODULE_DEVICE_TABLE(usb, rtw_8821cu_id_table); diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c index e6ab1ac6d709..a0188511099a 100644 --- a/drivers/net/wireless/realtek/rtw88/usb.c +++ b/drivers/net/wireless/realtek/rtw88/usb.c @@ -33,6 +33,36 @@ static void rtw_usb_fill_tx_checksum(struct rtw_usb *rtwusb, rtw_tx_fill_txdesc_checksum(rtwdev, &pkt_info, skb->data); } +static void rtw_usb_reg_sec(struct rtw_dev *rtwdev, u32 addr, __le32 *data) +{ + struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev); + struct usb_device *udev = rtwusb->udev; + bool reg_on_section = false; + u16 t_reg = 0x4e0; + u8 t_len = 1; + int status; + + /* There are three sections: + * 1. on (0x00~0xFF; 0x1000~0x10FF): this section is always powered on + * 2. off (< 0xFE00, excluding "on" section): this section could be + * powered off + * 3. local (>= 0xFE00): usb specific registers section + */ + if (addr <= 0xff || (addr >= 0x1000 && addr <= 0x10ff)) + reg_on_section = true; + + if (!reg_on_section) + return; + + status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + RTW_USB_CMD_REQ, RTW_USB_CMD_WRITE, + t_reg, 0, data, t_len, 500); + + if (status != t_len && status != -ENODEV) + rtw_err(rtwdev, "%s: reg 0x%x, usb write %u fail, status: %d\n", + __func__, t_reg, t_len, status); +} + static u32 rtw_usb_read(struct rtw_dev *rtwdev, u32 addr, u16 len) { struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev); @@ -58,6 +88,11 @@ static u32 rtw_usb_read(struct rtw_dev *rtwdev, u32 addr, u16 len) rtw_err(rtwdev, "read register 0x%x failed with %d\n", addr, ret); + if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C || + rtwdev->chip->id == RTW_CHIP_TYPE_8822B || + rtwdev->chip->id == RTW_CHIP_TYPE_8821C) + rtw_usb_reg_sec(rtwdev, addr, data); + return le32_to_cpu(*data); } @@ -102,6 +137,11 @@ static void rtw_usb_write(struct rtw_dev *rtwdev, u32 addr, u32 val, int len) if (ret < 0 && ret != -ENODEV && count++ < 4) rtw_err(rtwdev, "write register 0x%x failed with %d\n", addr, ret); + + if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C || + rtwdev->chip->id == RTW_CHIP_TYPE_8822B || + rtwdev->chip->id == RTW_CHIP_TYPE_8821C) + rtw_usb_reg_sec(rtwdev, addr, data); } static void rtw_usb_write8(struct rtw_dev *rtwdev, u32 addr, u8 val) diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c index f37afb4cbb63..d9b66d43f32e 100644 --- a/drivers/net/wireless/realtek/rtw89/coex.c +++ b/drivers/net/wireless/realtek/rtw89/coex.c @@ -129,68 +129,75 @@ static const u32 cxtbl[] = { static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = { /* firmware version must be in decreasing order for each chip */ + {RTL8922A, RTW89_FW_VER_CODE(0, 35, 8, 0), + .fcxbtcrpt = 8, .fcxtdma = 7, .fcxslots = 7, .fcxcysta = 7, + .fcxstep = 7, .fcxnullsta = 7, .fcxmreg = 7, .fcxgpiodbg = 7, + .fcxbtver = 7, .fcxbtscan = 7, .fcxbtafh = 7, .fcxbtdevinfo = 7, + .fwlrole = 2, .frptmap = 7, .fcxctrl = 7, .fcxinit = 7, + .drvinfo_type = 1, .info_buf = 1800, .max_role_num = 6, + }, {RTL8851B, RTW89_FW_VER_CODE(0, 29, 29, 0), .fcxbtcrpt = 105, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 5, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 2, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 2, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, - .info_buf = 1800, .max_role_num = 6, + .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1800, .max_role_num = 6, }, {RTL8852C, RTW89_FW_VER_CODE(0, 27, 57, 0), .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, - .info_buf = 1280, .max_role_num = 5, + .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1280, .max_role_num = 5, }, {RTL8852C, RTW89_FW_VER_CODE(0, 27, 42, 0), .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 2, .fcxctrl = 1, - .info_buf = 1280, .max_role_num = 5, + .fwlrole = 1, .frptmap = 2, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1280, .max_role_num = 5, }, {RTL8852C, RTW89_FW_VER_CODE(0, 27, 0, 0), .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 2, .fcxctrl = 1, - .info_buf = 1280, .max_role_num = 5, + .fwlrole = 1, .frptmap = 2, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1280, .max_role_num = 5, }, {RTL8852B, RTW89_FW_VER_CODE(0, 29, 29, 0), .fcxbtcrpt = 105, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 5, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 2, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 2, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, - .info_buf = 1800, .max_role_num = 6, + .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1800, .max_role_num = 6, }, {RTL8852B, RTW89_FW_VER_CODE(0, 29, 14, 0), .fcxbtcrpt = 5, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 4, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, - .info_buf = 1800, .max_role_num = 6, + .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1800, .max_role_num = 6, }, {RTL8852B, RTW89_FW_VER_CODE(0, 27, 0, 0), .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 1, .fcxctrl = 1, - .info_buf = 1280, .max_role_num = 5, + .fwlrole = 1, .frptmap = 1, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1280, .max_role_num = 5, }, {RTL8852A, RTW89_FW_VER_CODE(0, 13, 37, 0), .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, - .info_buf = 1280, .max_role_num = 5, + .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1280, .max_role_num = 5, }, {RTL8852A, RTW89_FW_VER_CODE(0, 13, 0, 0), .fcxbtcrpt = 1, .fcxtdma = 1, .fcxslots = 1, .fcxcysta = 2, .fcxstep = 2, .fcxnullsta = 1, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, - .fwlrole = 0, .frptmap = 0, .fcxctrl = 0, - .info_buf = 1024, .max_role_num = 5, + .fwlrole = 0, .frptmap = 0, .fcxctrl = 0, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1024, .max_role_num = 5, }, /* keep it to be the last as default entry */ @@ -198,8 +205,8 @@ static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = { .fcxbtcrpt = 1, .fcxtdma = 1, .fcxslots = 1, .fcxcysta = 2, .fcxstep = 2, .fcxnullsta = 1, .fcxmreg = 1, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, - .fwlrole = 0, .frptmap = 0, .fcxctrl = 0, - .info_buf = 1024, .max_role_num = 5, + .fwlrole = 0, .frptmap = 0, .fcxctrl = 0, .fcxinit = 0, + .drvinfo_type = 0, .info_buf = 1024, .max_role_num = 5, }, }; @@ -351,17 +358,26 @@ enum btc_cx_poicy_type { /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ BTC_CXP_OFF_EQ3 = (BTC_CXP_OFF << 8) | 5, + /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ + BTC_CXP_OFF_EQ4 = (BTC_CXP_OFF << 8) | 6, + + /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ + BTC_CXP_OFF_EQ5 = (BTC_CXP_OFF << 8) | 7, + /* TDMA off + pri: BT_Hi > WL > BT_Lo */ - BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 6, + BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 8, /* TDMA off + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */ - BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 7, + BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 9, /* TDMA off + pri: WL_Hi-Tx > BT, BT_Hi > other-WL > BT_Lo */ - BTC_CXP_OFF_BWB2 = (BTC_CXP_OFF << 8) | 8, + BTC_CXP_OFF_BWB2 = (BTC_CXP_OFF << 8) | 10, /* TDMA off + pri: WL_Hi-Tx = BT */ - BTC_CXP_OFF_BWB3 = (BTC_CXP_OFF << 8) | 9, + BTC_CXP_OFF_BWB3 = (BTC_CXP_OFF << 8) | 11, + + /* TDMA off + pri: WL > BT, Block-BT*/ + BTC_CXP_OFF_WL2 = (BTC_CXP_OFF << 8) | 12, /* TDMA off+Bcn-Protect + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo*/ BTC_CXP_OFFB_BWB0 = (BTC_CXP_OFFB << 8) | 0, @@ -676,20 +692,25 @@ static void _run_coex(struct rtw89_dev *rtwdev, static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state); static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update); -static void _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, - void *param, u16 len) +static int _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, + void *param, u16 len) { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; struct rtw89_btc_cx *cx = &btc->cx; struct rtw89_btc_wl_info *wl = &cx->wl; + struct rtw89_btc_dm *dm = &btc->dm; int ret; - if (!wl->status.map.init_ok) { + if (len > BTC_H2C_MAXLEN || len == 0) { + btc->fwinfo.cnt_h2c_fail++; + dm->error.map.h2c_buffer_over = true; + return -EINVAL; + } else if (!wl->status.map.init_ok) { rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): return by btc not init!!\n", __func__); pfwinfo->cnt_h2c_fail++; - return; + return -EINVAL; } else if ((wl->status.map.rf_off_pre == BTC_LPS_RF_OFF && wl->status.map.rf_off == BTC_LPS_RF_OFF) || (wl->status.map.lps_pre == BTC_LPS_RF_OFF && @@ -697,20 +718,23 @@ static void _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): return by wl off!!\n", __func__); pfwinfo->cnt_h2c_fail++; - return; + return -EINVAL; } - pfwinfo->cnt_h2c++; - ret = rtw89_fw_h2c_raw_with_hdr(rtwdev, h2c_class, h2c_func, param, len, false, true); - if (ret != 0) + if (ret) pfwinfo->cnt_h2c_fail++; + else + pfwinfo->cnt_h2c++; + + return ret; } static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; + const struct rtw89_btc_ver *ver = btc->ver; struct rtw89_btc_cx *cx = &btc->cx; struct rtw89_btc_wl_info *wl = &btc->cx.wl; struct rtw89_btc_bt_info *bt = &btc->cx.bt; @@ -728,7 +752,9 @@ static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) if (type & BTC_RESET_CTRL) { memset(&btc->ctrl, 0, sizeof(btc->ctrl)); - btc->ctrl.trace_step = FCXDEF_STEP; + btc->manual_ctrl = false; + if (ver->fcxctrl != 7) + btc->ctrl.ctrl.trace_step = FCXDEF_STEP; } /* Init Coex variables that are not zero */ @@ -777,22 +803,27 @@ static void _get_reg_status(struct rtw89_dev *rtwdev, u8 type, u8 *val) { struct rtw89_btc *btc = &rtwdev->btc; const struct rtw89_btc_ver *ver = btc->ver; - struct rtw89_btc_module *md = &btc->mdinfo; + union rtw89_btc_module_info *md = &btc->mdinfo; union rtw89_btc_fbtc_mreg_val *pmreg; u32 pre_agc_addr = R_BTC_BB_PRE_AGC_S1; u32 reg_val; - u8 idx; + u8 idx, switch_type; - if (md->ant.btg_pos == RF_PATH_A) + if (ver->fcxinit == 7) + switch_type = md->md_v7.switch_type; + else + switch_type = md->md.switch_type; + + if (btc->btg_pos == RF_PATH_A) pre_agc_addr = R_BTC_BB_PRE_AGC_S0; switch (type) { case BTC_CSTATUS_TXDIV_POS: - if (md->switch_type == BTC_SWITCH_INTERNAL) + if (switch_type == BTC_SWITCH_INTERNAL) *val = BTC_ANT_DIV_MAIN; break; case BTC_CSTATUS_RXDIV_POS: - if (md->switch_type == BTC_SWITCH_INTERNAL) + if (switch_type == BTC_SWITCH_INTERNAL) *val = BTC_ANT_DIV_MAIN; break; case BTC_CSTATUS_BB_GNT_MUX: @@ -1117,7 +1148,7 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev, void *rpt_content = NULL, *pfinfo = NULL; u8 rpt_type = 0; u16 wl_slot_set = 0, wl_slot_real = 0; - u32 trace_step = btc->ctrl.trace_step, rpt_len = 0, diff_t = 0; + u32 trace_step = 0, rpt_len = 0, diff_t = 0; u32 cnt_leak_slot, bt_slot_real, bt_slot_set, cnt_rx_imr; u8 i, val = 0; @@ -1207,6 +1238,9 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev, break; case BTC_RPT_TYPE_STEP: pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; + if (ver->fcxctrl != 7) + trace_step = btc->ctrl.ctrl.trace_step; + if (ver->fcxstep == 2) { pfinfo = &pfwinfo->rpt_fbtc_step.finfo.v2; pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_step.finfo.v2.step[0]) * @@ -1920,6 +1954,7 @@ static void rtw89_btc_fw_en_rpt(struct rtw89_dev *rtwdev, struct rtw89_btc_btf_fwinfo *fwinfo = &btc->fwinfo; struct rtw89_btc_btf_set_report r = {0}; u32 val, bit_map; + int ret; if ((wl_smap->rf_off || wl_smap->lps != BTC_LPS_OFF) && rpt_state != 0) return; @@ -1938,13 +1973,13 @@ static void rtw89_btc_fw_en_rpt(struct rtw89_dev *rtwdev, if (val == fwinfo->rpt_en_map) return; - fwinfo->rpt_en_map = val; - r.fver = BTF_SET_REPORT_VER; r.enable = cpu_to_le32(val); r.para = cpu_to_le32(rpt_state); - _send_fw_cmd(rtwdev, BTFC_SET, SET_REPORT_EN, &r, sizeof(r)); + ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_REPORT_EN, &r, sizeof(r)); + if (!ret) + fwinfo->rpt_en_map = val; } static void rtw89_btc_fw_set_slots(struct rtw89_dev *rtwdev, u8 num, @@ -2032,6 +2067,7 @@ static void _fw_set_policy(struct rtw89_dev *rtwdev, u16 policy_type, { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_dm *dm = &btc->dm; + int ret; dm->run_action = action; @@ -2060,11 +2096,12 @@ static void _fw_set_policy(struct rtw89_dev *rtwdev, u16 policy_type, if (btc->lps == 1) rtw89_set_coex_ctrl_lps(rtwdev, btc->lps); - _send_fw_cmd(rtwdev, BTFC_SET, SET_CX_POLICY, - btc->policy, btc->policy_len); - - memcpy(&dm->tdma_now, &dm->tdma, sizeof(dm->tdma_now)); - memcpy(&dm->slot_now, &dm->slot, sizeof(dm->slot_now)); + ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_CX_POLICY, + btc->policy, btc->policy_len); + if (!ret) { + memcpy(&dm->tdma_now, &dm->tdma, sizeof(dm->tdma_now)); + memcpy(&dm->slot_now, &dm->slot, sizeof(dm->slot_now)); + } if (btc->update_policy_force) btc->update_policy_force = false; @@ -2083,20 +2120,32 @@ static void _fw_set_drv_info(struct rtw89_dev *rtwdev, u8 type) switch (type) { case CXDRVINFO_INIT: - rtw89_fw_h2c_cxdrv_init(rtwdev); + if (ver->fcxinit == 7) + rtw89_fw_h2c_cxdrv_init_v7(rtwdev, type); + else + rtw89_fw_h2c_cxdrv_init(rtwdev, type); break; case CXDRVINFO_ROLE: if (ver->fwlrole == 0) - rtw89_fw_h2c_cxdrv_role(rtwdev); + rtw89_fw_h2c_cxdrv_role(rtwdev, type); else if (ver->fwlrole == 1) - rtw89_fw_h2c_cxdrv_role_v1(rtwdev); + rtw89_fw_h2c_cxdrv_role_v1(rtwdev, type); else if (ver->fwlrole == 2) - rtw89_fw_h2c_cxdrv_role_v2(rtwdev); + rtw89_fw_h2c_cxdrv_role_v2(rtwdev, type); break; case CXDRVINFO_CTRL: - rtw89_fw_h2c_cxdrv_ctrl(rtwdev); + if (ver->drvinfo_type == 1) + type = 2; + + if (ver->fcxctrl == 7) + rtw89_fw_h2c_cxdrv_ctrl_v7(rtwdev, type); + else + rtw89_fw_h2c_cxdrv_ctrl(rtwdev, type); break; case CXDRVINFO_TRX: + if (ver->drvinfo_type == 1) + type = 3; + dm->trx_info.tx_power = u32_get_bits(rf_para.wl_tx_power, RTW89_BTC_WL_DEF_TX_PWR); dm->trx_info.rx_gain = u32_get_bits(rf_para.wl_rx_gain, @@ -2107,11 +2156,18 @@ static void _fw_set_drv_info(struct rtw89_dev *rtwdev, u8 type) RTW89_BTC_WL_DEF_TX_PWR); dm->trx_info.cn = wl->cn_report; dm->trx_info.nhm = wl->nhm.pwr; - rtw89_fw_h2c_cxdrv_trx(rtwdev); + rtw89_fw_h2c_cxdrv_trx(rtwdev, type); break; case CXDRVINFO_RFK: - rtw89_fw_h2c_cxdrv_rfk(rtwdev); + if (ver->drvinfo_type == 1) + return; + + rtw89_fw_h2c_cxdrv_rfk(rtwdev, type); break; + case CXDRVINFO_TXPWR: + case CXDRVINFO_FDDT: + case CXDRVINFO_MLO: + case CXDRVINFO_OSI: default: break; } @@ -2261,20 +2317,25 @@ static void _set_bt_tx_power(struct rtw89_dev *rtwdev, u8 level) { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_bt_info *bt = &btc->cx.bt; + int ret; u8 buf; - if (bt->rf_para.tx_pwr_freerun == level) + if (btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE] == 0) return; - bt->rf_para.tx_pwr_freerun = level; - btc->dm.rf_trx_para.bt_tx_power = level; + if (bt->rf_para.tx_pwr_freerun == level) + return; rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): level = %d\n", __func__, level); buf = (s8)(-level); - _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_TX_PWR, &buf, 1); + ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_TX_PWR, &buf, 1); + if (!ret) { + bt->rf_para.tx_pwr_freerun = level; + btc->dm.rf_trx_para.bt_tx_power = level; + } } #define BTC_BT_RX_NORMAL_LVL 7 @@ -2284,6 +2345,9 @@ static void _set_bt_rx_gain(struct rtw89_dev *rtwdev, u8 level) struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_bt_info *bt = &btc->cx.bt; + if (btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE] == 0) + return; + if ((bt->rf_para.rx_gain_freerun == level || level > BTC_BT_RX_NORMAL_LVL) && (!rtwdev->chip->scbd || bt->lna_constrain == level)) @@ -2333,7 +2397,7 @@ static void _set_rf_trx_para(struct rtw89_dev *rtwdev) } /* decide trx_para_level */ - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { /* fix LNA2 + TIA gain not change by GNT_BT */ if ((btc->dm.wl_btg_rx && b->profile_cnt.now != 0) || dm->bt_only == 1) @@ -2435,7 +2499,7 @@ static void _set_bt_afh_info(struct rtw89_dev *rtwdev) u8 en = 0, i, ch = 0, bw = 0; u8 mode, connect_cnt; - if (btc->ctrl.manual || wl->status.map.scan) + if (btc->manual_ctrl || wl->status.map.scan) return; if (ver->fwlrole == 0) { @@ -2560,8 +2624,16 @@ static bool _check_freerun(struct rtw89_dev *rtwdev) struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; struct rtw89_btc_bt_hid_desc *hid = &bt_linfo->hid_desc; + union rtw89_btc_module_info *md = &btc->mdinfo; + const struct rtw89_btc_ver *ver = btc->ver; + u8 isolation; + + if (ver->fcxinit == 7) + isolation = md->md_v7.ant.isolation; + else + isolation = md->md.ant.isolation; - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { btc->dm.trx_para_level = 0; return false; } @@ -2584,7 +2656,7 @@ static bool _check_freerun(struct rtw89_dev *rtwdev) } /* TODO get isolation by BT psd */ - if (btc->mdinfo.ant.isolation >= BTC_FREERUN_ANTISO_MIN) { + if (isolation >= BTC_FREERUN_ANTISO_MIN) { btc->dm.trx_para_level = 5; return true; } @@ -2712,7 +2784,7 @@ void rtw89_btc_set_policy(struct rtw89_dev *rtwdev, u16 policy_type) u8 type; u32 tbl_w1, tbl_b1, tbl_b4; - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { if (btc->cx.wl.status.map._4way) tbl_w1 = cxtbl[1]; else @@ -3023,12 +3095,13 @@ void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type) struct rtw89_btc_wl_role_info_v1 *wl_rinfo = &btc->cx.wl.role_info_v1; struct rtw89_btc_bt_hid_desc *hid = &btc->cx.bt.link_info.hid_desc; struct rtw89_btc_bt_hfp_desc *hfp = &btc->cx.bt.link_info.hfp_desc; + struct rtw89_btc_wl_info *wl = &btc->cx.wl; u8 type, null_role; u32 tbl_w1, tbl_b1, tbl_b4; type = FIELD_GET(BTC_CXP_MASK, policy_type); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { if (btc->cx.wl.status.map._4way) tbl_w1 = cxtbl[1]; else if (hid->exist && hid->type == BTC_HID_218) @@ -3048,9 +3121,16 @@ void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type) tbl_b4 = cxtbl[2]; } } else { - tbl_w1 = cxtbl[16]; tbl_b1 = cxtbl[17]; tbl_b4 = cxtbl[17]; + + if (wl->bg_mode) + tbl_w1 = cxtbl[8]; + else if ((wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) && + hid->exist) + tbl_w1 = cxtbl[19]; + else + tbl_w1 = cxtbl[16]; } btc->bt_req_en = false; @@ -3615,7 +3695,7 @@ static void _action_bt_idle(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ switch (btc->cx.state_map) { case BTC_WBUSY_BNOSCAN: /*wl-busy + bt idle*/ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */ @@ -3654,7 +3734,7 @@ static void _action_bt_hfp(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { if (btc->cx.wl.status.map._4way) { _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_BT_HFP); } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { @@ -3664,7 +3744,12 @@ static void _action_bt_hfp(struct rtw89_dev *rtwdev) _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_BT_HFP); } } else { - _set_policy(rtwdev, BTC_CXP_OFF_EQ2, BTC_ACT_BT_HFP); + if (wl->bg_mode) + _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_BT_HFP); + else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) + _set_policy(rtwdev, BTC_CXP_OFF_EQ5, BTC_ACT_BT_HFP); + else + _set_policy(rtwdev, BTC_CXP_OFF_EQ2, BTC_ACT_BT_HFP); } } @@ -3679,7 +3764,7 @@ static void _action_bt_hid(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ if (wl->status.map._4way) { policy_type = BTC_CXP_OFF_WL; } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { @@ -3697,7 +3782,12 @@ static void _action_bt_hid(struct rtw89_dev *rtwdev) policy_type = BTC_CXP_OFF_BWB1; } } else { /* dedicated-antenna */ - policy_type = BTC_CXP_OFF_EQ3; + if (wl->bg_mode) + policy_type = BTC_CXP_OFF_BWB1; + else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) + policy_type = BTC_CXP_OFF_EQ4; + else + policy_type = BTC_CXP_OFF_EQ3; } _set_policy(rtwdev, policy_type, BTC_ACT_BT_HID); @@ -3947,7 +4037,7 @@ static void _action_wl_other(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) + if (btc->ant_type == BTC_ANT_SHARED) _set_policy(rtwdev, BTC_CXP_OFFB_BWB0, BTC_ACT_WL_OTHER); else _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_OTHER); @@ -3991,7 +4081,7 @@ static void _set_btg_ctrl(struct rtw89_dev *rtwdev) u32 is_btg; u8 i, val; - if (btc->ctrl.manual) + if (btc->manual_ctrl) return; if (ver->fwlrole == 0) @@ -4063,7 +4153,7 @@ static void _set_wl_preagc_ctrl(struct rtw89_dev *rtwdev) struct rtw89_btc_dm *dm = &btc->dm; u8 is_preagc, val; - if (btc->ctrl.manual) + if (btc->manual_ctrl) return; if (wl_rinfo->link_mode == BTC_WLINK_25G_MCC) @@ -4083,7 +4173,7 @@ static void _set_wl_preagc_ctrl(struct rtw89_dev *rtwdev) else if (ver->fwlrole == 2 && wl_rinfo->dbcc_en && wl_rinfo->dbcc_2g_phy != RTW89_PHY_1) is_preagc = BTC_PREAGC_DISABLE; - else if (btc->mdinfo.ant.type == BTC_ANT_SHARED) + else if (btc->ant_type == BTC_ANT_SHARED) is_preagc = BTC_PREAGC_DISABLE; else is_preagc = BTC_PREAGC_ENABLE; @@ -4187,13 +4277,12 @@ static void _set_wl_tx_limit(struct rtw89_dev *rtwdev) struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; struct rtw89_txtime_data data = {.rtwdev = rtwdev}; - u8 mode; - u8 tx_retry; + u8 mode, igno_bt, tx_retry; u32 tx_time; u16 enable; bool reenable = false; - if (btc->ctrl.manual) + if (btc->manual_ctrl) return; if (ver->fwlrole == 0) @@ -4205,7 +4294,12 @@ static void _set_wl_tx_limit(struct rtw89_dev *rtwdev) else return; - if (btc->dm.freerun || btc->ctrl.igno_bt || b->profile_cnt.now == 0 || + if (ver->fcxctrl == 7) + igno_bt = btc->ctrl.ctrl_v7.igno_bt; + else + igno_bt = btc->ctrl.ctrl.igno_bt; + + if (btc->dm.freerun || igno_bt || b->profile_cnt.now == 0 || mode == BTC_WLINK_5G || mode == BTC_WLINK_NOLINK) { enable = 0; tx_time = BTC_MAX_TX_TIME_DEF; @@ -4402,7 +4496,7 @@ static void _action_wl_scan(struct rtw89_dev *rtwdev) if (RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W25G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) + if (btc->ant_type == BTC_ANT_SHARED) _set_policy(rtwdev, BTC_CXP_OFFE_DEF, BTC_RSN_NTFY_SCAN_START); else @@ -4430,7 +4524,7 @@ static void _action_wl_25g_mcc(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W25G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { if (btc->cx.bt.link_info.profile_cnt.now == 0) _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, BTC_ACT_WL_25G_MCC); @@ -4447,7 +4541,7 @@ static void _action_wl_2g_mcc(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ if (btc->cx.bt.link_info.profile_cnt.now == 0) _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_MCC); @@ -4465,7 +4559,7 @@ static void _action_wl_2g_scc(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ if (btc->cx.bt.link_info.profile_cnt.now == 0) _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_SCC); @@ -4487,7 +4581,7 @@ static void _action_wl_2g_scc_v1(struct rtw89_dev *rtwdev) u16 policy_type = BTC_CXP_OFF_BT; u32 dur; - if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED) { + if (btc->ant_type == BTC_ANT_DEDICATED) { policy_type = BTC_CXP_OFF_EQ0; } else { /* shared-antenna */ @@ -4549,7 +4643,7 @@ static void _action_wl_2g_scc_v2(struct rtw89_dev *rtwdev) u16 policy_type = BTC_CXP_OFF_BT; u32 dur; - if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED) { + if (btc->ant_type == BTC_ANT_DEDICATED) { policy_type = BTC_CXP_OFF_EQ0; } else { /* shared-antenna */ @@ -4607,7 +4701,7 @@ static void _action_wl_2g_ap(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { if (btc->cx.bt.link_info.profile_cnt.now == 0) _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_AP); @@ -4624,7 +4718,7 @@ static void _action_wl_2g_go(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ if (btc->cx.bt.link_info.profile_cnt.now == 0) _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_GO); @@ -4642,7 +4736,7 @@ static void _action_wl_2g_gc(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ _action_by_bt(rtwdev); } else {/* dedicated-antenna */ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_GC); @@ -4655,7 +4749,7 @@ static void _action_wl_2g_nan(struct rtw89_dev *rtwdev) _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); - if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ + if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ if (btc->cx.bt.link_info.profile_cnt.now == 0) _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_NAN); @@ -5351,7 +5445,7 @@ void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; - u8 mode; + u8 mode, igno_bt, always_freerun; lockdep_assert_held(&rtwdev->mutex); @@ -5368,20 +5462,28 @@ void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) else return; + if (ver->fcxctrl == 7) { + igno_bt = btc->ctrl.ctrl_v7.igno_bt; + always_freerun = btc->ctrl.ctrl_v7.always_freerun; + } else { + igno_bt = btc->ctrl.ctrl.igno_bt; + always_freerun = btc->ctrl.ctrl.always_freerun; + } + rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): reason=%d, mode=%d\n", __func__, reason, mode); rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): wl_only=%d, bt_only=%d\n", __func__, dm->wl_only, dm->bt_only); /* Be careful to change the following function sequence!! */ - if (btc->ctrl.manual) { + if (btc->manual_ctrl) { rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): return for Manual CTRL!!\n", __func__); return; } - if (btc->ctrl.igno_bt && + if (igno_bt && (reason == BTC_RSN_UPDATE_BT_INFO || reason == BTC_RSN_UPDATE_BT_SCBD)) { rtw89_debug(rtwdev, RTW89_DBG_BTC, @@ -5418,24 +5520,24 @@ void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) dm->freerun = false; dm->cnt_dm[BTC_DCNT_RUN]++; dm->fddt_train = BTC_FDDT_DISABLE; - btc->ctrl.igno_bt = false; bt->scan_rx_low_pri = false; + igno_bt = false; - if (btc->ctrl.always_freerun) { + if (always_freerun) { _action_freerun(rtwdev); - btc->ctrl.igno_bt = true; + igno_bt = true; goto exit; } if (dm->wl_only) { _action_wl_only(rtwdev); - btc->ctrl.igno_bt = true; + igno_bt = true; goto exit; } if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) { _action_wl_off(rtwdev, mode); - btc->ctrl.igno_bt = true; + igno_bt = true; goto exit; } @@ -5525,6 +5627,10 @@ void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) exit: rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): exit\n", __func__); + if (ver->fcxctrl == 7) + btc->ctrl.ctrl_v7.igno_bt = igno_bt; + else + btc->ctrl.ctrl.igno_bt = igno_bt; _action_common(rtwdev); } @@ -5560,16 +5666,26 @@ static void _set_init_info(struct rtw89_dev *rtwdev) { const struct rtw89_chip_info *chip = rtwdev->chip; struct rtw89_btc *btc = &rtwdev->btc; + const struct rtw89_btc_ver *ver = btc->ver; struct rtw89_btc_dm *dm = &btc->dm; struct rtw89_btc_wl_info *wl = &btc->cx.wl; - dm->init_info.wl_only = (u8)dm->wl_only; - dm->init_info.bt_only = (u8)dm->bt_only; - dm->init_info.wl_init_ok = (u8)wl->status.map.init_ok; - dm->init_info.dbcc_en = rtwdev->dbcc_en; - dm->init_info.cx_other = btc->cx.other.type; - dm->init_info.wl_guard_ch = chip->afh_guard_ch; - dm->init_info.module = btc->mdinfo; + if (ver->fcxinit == 7) { + dm->init_info.init_v7.wl_only = (u8)dm->wl_only; + dm->init_info.init_v7.bt_only = (u8)dm->bt_only; + dm->init_info.init_v7.wl_init_ok = (u8)wl->status.map.init_ok; + dm->init_info.init_v7.cx_other = btc->cx.other.type; + dm->init_info.init_v7.wl_guard_ch = chip->afh_guard_ch; + dm->init_info.init_v7.module = btc->mdinfo.md_v7; + } else { + dm->init_info.init.wl_only = (u8)dm->wl_only; + dm->init_info.init.bt_only = (u8)dm->bt_only; + dm->init_info.init.wl_init_ok = (u8)wl->status.map.init_ok; + dm->init_info.init.dbcc_en = rtwdev->dbcc_en; + dm->init_info.init.cx_other = btc->cx.other.type; + dm->init_info.init.wl_guard_ch = chip->afh_guard_ch; + dm->init_info.init.module = btc->mdinfo.md; + } } void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode) @@ -5578,11 +5694,15 @@ void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode) struct rtw89_btc_dm *dm = &rtwdev->btc.dm; struct rtw89_btc_wl_info *wl = &btc->cx.wl; const struct rtw89_chip_info *chip = rtwdev->chip; + const struct rtw89_btc_ver *ver = btc->ver; _reset_btc_var(rtwdev, BTC_RESET_ALL); btc->dm.run_reason = BTC_RSN_NONE; btc->dm.run_action = BTC_ACT_NONE; - btc->ctrl.igno_bt = true; + if (ver->fcxctrl == 7) + btc->ctrl.ctrl_v7.igno_bt = true; + else + btc->ctrl.ctrl.igno_bt = true; rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): mode=%d\n", __func__, mode); @@ -6298,7 +6418,7 @@ static void rtw89_btc_ntfy_wl_sta_iter(void *data, struct ieee80211_sta *sta) if (BTC_RSSI_LOW(link_info->rssi_state[i])) rssi_map |= BIT(i); - if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED && + if (btc->ant_type == BTC_ANT_DEDICATED && BTC_RSSI_CHANGE(link_info->rssi_state[i])) is_sta_change = true; } @@ -6489,13 +6609,16 @@ void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, static void _show_cx_info(struct rtw89_dev *rtwdev, struct seq_file *m) { + union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; const struct rtw89_chip_info *chip = rtwdev->chip; + const struct rtw89_btc_ver *ver = rtwdev->btc.ver; struct rtw89_hal *hal = &rtwdev->hal; struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_dm *dm = &btc->dm; struct rtw89_btc_bt_info *bt = &btc->cx.bt; struct rtw89_btc_wl_info *wl = &btc->cx.wl; u32 ver_main = 0, ver_sub = 0, ver_hotfix = 0, id_branch = 0; + u8 cv, rfe, iso, ant_num, ant_single_pos; if (!(dm->coex_info_map & BTC_COEX_INFO_CX)) return; @@ -6545,11 +6668,24 @@ static void _show_cx_info(struct rtw89_dev *rtwdev, struct seq_file *m) ver_main, ver_sub, ver_hotfix, id_branch, bt->ver_info.fw, bt->run_patch_code ? "patch" : "ROM"); + if (ver->fcxinit == 7) { + cv = md->md_v7.kt_ver; + rfe = md->md_v7.rfe_type; + iso = md->md_v7.ant.isolation; + ant_num = md->md_v7.ant.num; + ant_single_pos = md->md_v7.ant.single_pos; + } else { + cv = md->md.cv; + rfe = md->md.rfe_type; + iso = md->md.ant.isolation; + ant_num = md->md.ant.num; + ant_single_pos = md->md.ant.single_pos; + } + seq_printf(m, " %-15s : cv:%x, rfe_type:0x%x, ant_iso:%d, ant_pg:%d, %s", - "[hw_info]", btc->mdinfo.cv, btc->mdinfo.rfe_type, - btc->mdinfo.ant.isolation, btc->mdinfo.ant.num, - (btc->mdinfo.ant.num > 1 ? "" : (btc->mdinfo.ant.single_pos ? - "1Ant_Pos:S1, " : "1Ant_Pos:S0, "))); + "[hw_info]", cv, rfe, iso, ant_num, + ant_num > 1 ? "" : + ant_single_pos ? "1Ant_Pos:S1, " : "1Ant_Pos:S0, "); seq_printf(m, "3rd_coex:%d, dbcc:%d, tx_num:%d, rx_num:%d\n", btc->cx.other.type, rtwdev->dbcc_en, hal->tx_nss, @@ -6722,20 +6858,26 @@ static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) struct rtw89_btc_cx *cx = &btc->cx; struct rtw89_btc_bt_info *bt = &cx->bt; struct rtw89_btc_wl_info *wl = &cx->wl; - struct rtw89_btc_module *module = &btc->mdinfo; struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; + union rtw89_btc_module_info *md = &btc->mdinfo; u8 *afh = bt_linfo->afh_map; u8 *afh_le = bt_linfo->afh_map_le; + u8 bt_pos; if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT)) return; + if (ver->fcxinit == 7) + bt_pos = md->md_v7.bt_pos; + else + bt_pos = md->md.bt_pos; + seq_puts(m, "========== [BT Status] ==========\n"); seq_printf(m, " %-15s : enable:%s, btg:%s%s, connect:%s, ", "[status]", bt->enable.now ? "Y" : "N", bt->btg_type ? "Y" : "N", - (bt->enable.now && (bt->btg_type != module->bt_pos) ? + (bt->enable.now && (bt->btg_type != bt_pos) ? "(efuse-mismatch!!)" : ""), (bt_linfo->status.map.connect ? "Y" : "N")); @@ -6934,10 +7076,13 @@ static const char *steps_to_str(u16 step) CASE_BTC_POLICY_STR(OFF_EQ1); CASE_BTC_POLICY_STR(OFF_EQ2); CASE_BTC_POLICY_STR(OFF_EQ3); + CASE_BTC_POLICY_STR(OFF_EQ4); + CASE_BTC_POLICY_STR(OFF_EQ5); CASE_BTC_POLICY_STR(OFF_BWB0); CASE_BTC_POLICY_STR(OFF_BWB1); CASE_BTC_POLICY_STR(OFF_BWB2); CASE_BTC_POLICY_STR(OFF_BWB3); + CASE_BTC_POLICY_STR(OFF_WL2); CASE_BTC_POLICY_STR(OFFB_BWB0); CASE_BTC_POLICY_STR(OFFE_DEF); CASE_BTC_POLICY_STR(OFFE_DEF2); @@ -7123,21 +7268,22 @@ static void _show_dm_step(struct rtw89_dev *rtwdev, struct seq_file *m) static void _show_dm_info(struct rtw89_dev *rtwdev, struct seq_file *m) { struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; + const struct rtw89_btc_ver *ver = btc->ver; struct rtw89_btc_dm *dm = &btc->dm; struct rtw89_btc_wl_info *wl = &btc->cx.wl; struct rtw89_btc_bt_info *bt = &btc->cx.bt; + u8 igno_bt; if (!(dm->coex_info_map & BTC_COEX_INFO_DM)) return; seq_printf(m, "========== [Mechanism Status %s] ==========\n", - (btc->ctrl.manual ? "(Manual)" : "(Auto)")); + (btc->manual_ctrl ? "(Manual)" : "(Auto)")); seq_printf(m, " %-15s : type:%s, reason:%s(), action:%s(), ant_path:%s, init_mode:%s, run_cnt:%d\n", "[status]", - module->ant.type == BTC_ANT_SHARED ? "shared" : "dedicated", + btc->ant_type == BTC_ANT_SHARED ? "shared" : "dedicated", steps_to_str(dm->run_reason), steps_to_str(dm->run_action | BTC_ACT_EXT_BIT), id_to_ant(FIELD_GET(GENMASK(7, 0), dm->set_ant_path)), @@ -7146,8 +7292,13 @@ static void _show_dm_info(struct rtw89_dev *rtwdev, struct seq_file *m) _show_dm_step(rtwdev, m); + if (ver->fcxctrl == 7) + igno_bt = btc->ctrl.ctrl_v7.igno_bt; + else + igno_bt = btc->ctrl.ctrl.igno_bt; + seq_printf(m, " %-15s : wl_only:%d, bt_only:%d, igno_bt:%d, free_run:%d, wl_ps_ctrl:%d, wl_mimo_ps:%d, ", - "[dm_flag]", dm->wl_only, dm->bt_only, btc->ctrl.igno_bt, + "[dm_flag]", dm->wl_only, dm->bt_only, igno_bt, dm->freerun, btc->lps, dm->wl_mimo_ps); seq_printf(m, "leak_ap:%d, fw_offload:%s%s\n", dm->leak_ap, @@ -7888,10 +8039,11 @@ static void _show_fbtc_step_v2(struct rtw89_dev *rtwdev, struct seq_file *m) struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; struct rtw89_btc_fbtc_steps_v2 *pstep = NULL; + const struct rtw89_btc_ver *ver = btc->ver; u8 type, val, cnt = 0, state = 0; bool outloop = false; u16 i, diff_t, n_start = 0, n_stop = 0; - u16 pos_old, pos_new; + u16 pos_old, pos_new, trace_step; pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; if (!pcinfo->valid) @@ -7908,11 +8060,16 @@ static void _show_fbtc_step_v2(struct rtw89_dev *rtwdev, struct seq_file *m) do { switch (state) { case 0: + if (ver->fcxctrl == 7 || ver->fcxctrl == 1) + trace_step = 50; + else + trace_step = btc->ctrl.ctrl.trace_step; + n_start = pos_old; if (pos_new >= pos_old) n_stop = pos_new; else - n_stop = btc->ctrl.trace_step - 1; + n_stop = trace_step - 1; state = 1; break; @@ -8742,7 +8899,7 @@ void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m) seq_printf(m, "WL FW / BT FW %d.%d.%d.%d / NA\n", fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver, fw_suit->sub_idex); - seq_printf(m, "manual %d\n", btc->ctrl.manual); + seq_printf(m, "manual %d\n", btc->manual_ctrl); seq_puts(m, "=========================================\n"); diff --git a/drivers/net/wireless/realtek/rtw89/coex.h b/drivers/net/wireless/realtek/rtw89/coex.h index 08121fd899e6..13303830684e 100644 --- a/drivers/net/wireless/realtek/rtw89/coex.h +++ b/drivers/net/wireless/realtek/rtw89/coex.h @@ -7,6 +7,8 @@ #include "core.h" +#define BTC_H2C_MAXLEN 2020 + enum btc_mode { BTC_MODE_NORMAL, BTC_MODE_WL, @@ -153,6 +155,10 @@ enum btc_lps_state { #define BTC_REG_NOTFOUND 0xff +#define R_BTC_ZB_COEX_TBL_0 0xE328 +#define R_BTC_ZB_COEX_TBL_1 0xE32c +#define R_BTC_ZB_BREAK_TBL 0xE350 + enum btc_ant_div_pos { BTC_ANT_DIV_MAIN = 0, BTC_ANT_DIV_AUX = 1, @@ -181,6 +187,20 @@ enum btc_btgctrl_type { BTC_BTGCTRL_BB_GNT_NOTFOUND, }; +enum btc_wa_type { + BTC_WA_5G_HI_CH_RX = BIT(0), + BTC_WA_NULL_AP = BIT(1), + BTC_WA_HFP_ZB = BIT(2), /* HFP PTA req bit4 define issue */ +}; + +enum btc_3cx_type { + BTC_3CX_NONE = 0, + BTC_3CX_BT2 = BIT(0), + BTC_3CX_ZB = BIT(1), + BTC_3CX_LTE = BIT(2), + BTC_3CX_MAX, +}; + void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev); void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev); void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode); diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c index f697e3d898e6..d474b8d5df3d 100644 --- a/drivers/net/wireless/realtek/rtw89/core.c +++ b/drivers/net/wireless/realtek/rtw89/core.c @@ -3801,7 +3801,7 @@ static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, struct ieee80211_sta_eht_cap *eht_cap; struct rtw89_hal *hal = &rtwdev->hal; bool support_320mhz = false; - int sts = 3; + int sts = 8; u8 val; if (chip->chip_gen == RTW89_CHIP_AX) @@ -3845,18 +3845,16 @@ static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, eht_cap_elem->phy_cap_info[2] = 0; eht_cap_elem->phy_cap_info[3] = - IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | - IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | - IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK; + IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | + IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; eht_cap_elem->phy_cap_info[4] = IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); eht_cap_elem->phy_cap_info[5] = - IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); @@ -4505,6 +4503,8 @@ static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) hw->wiphy->max_remain_on_channel_duration = 1000; wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); + wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); + wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); ret = rtw89_core_set_supported_band(rtwdev); if (ret) { diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index d62d23015c48..2e854c9af709 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -1151,9 +1151,15 @@ struct rtw89_mac_ax_gnt { u8 gnt_wl; } __packed; +struct rtw89_mac_ax_wl_act { + u8 wlan_act_en; + u8 wlan_act; +}; + #define RTW89_MAC_AX_COEX_GNT_NR 2 struct rtw89_mac_ax_coex_gnt { struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; + struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; }; enum rtw89_btc_ncnt { @@ -1271,6 +1277,18 @@ struct rtw89_btc_ant_info { u8 stream_cnt: 4; }; +struct rtw89_btc_ant_info_v7 { + u8 type; /* shared, dedicated(non-shared) */ + u8 num; /* antenna count */ + u8 isolation; + u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ + + u8 diversity; /* only for wifi use 1-antenna */ + u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ + u8 stream_cnt; /* spatial_stream count */ + u8 rsvd; +} __packed; + enum rtw89_tfc_dir { RTW89_TFC_UL, RTW89_TFC_DL, @@ -1665,6 +1683,16 @@ struct rtw89_btc_dm_emap { u32 wl_e2g_hang: 1; u32 wl_ver_mismatch: 1; u32 bt_ver_mismatch: 1; + u32 rfe_type0: 1; + u32 h2c_buffer_over: 1; + u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ + u32 wl_no_sta_ntfy: 1; + + u32 h2c_bmap_mismatch: 1; + u32 c2h_bmap_mismatch: 1; + u32 h2c_struct_invalid: 1; + u32 c2h_struct_invalid: 1; + u32 h2c_c2h_buffer_mismatch: 1; }; union rtw89_btc_dm_error_map { @@ -1713,6 +1741,7 @@ struct rtw89_btc_wl_info { u8 cn_report; u8 coex_mode; + bool bg_mode; bool scbd_change; u32 scbd; }; @@ -1730,6 +1759,25 @@ struct rtw89_btc_module { u8 kt_ver_adie; }; +struct rtw89_btc_module_v7 { + u8 rfe_type; + u8 kt_ver; + u8 bt_solo; + u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ + + u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ + u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ + u8 kt_ver_adie; + u8 rsvd; + + struct rtw89_btc_ant_info_v7 ant; +} __packed; + +union rtw89_btc_module_info { + struct rtw89_btc_module md; + struct rtw89_btc_module_v7 md_v7; +}; + #define RTW89_BTC_DM_MAXSTEP 30 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) @@ -1752,6 +1800,25 @@ struct rtw89_btc_init_info { u16 rsvd; }; +struct rtw89_btc_init_info_v7 { + u8 wl_guard_ch; + u8 wl_only; + u8 wl_init_ok; + u8 rsvd3; + + u8 cx_other; + u8 bt_only; + u8 pta_mode; + u8 pta_direction; + + struct rtw89_btc_module_v7 module; +} __packed; + +union rtw89_btc_init_info_u { + struct rtw89_btc_init_info init; + struct rtw89_btc_init_info_v7 init_v7; +}; + struct rtw89_btc_wl_tx_limit_para { u16 enable; u32 tx_time; /* unit: us */ @@ -2490,7 +2557,7 @@ struct rtw89_btc_dm { struct rtw89_btc_fbtc_tdma tdma; struct rtw89_btc_fbtc_tdma tdma_now; struct rtw89_mac_ax_coex_gnt gnt; - struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ + union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ struct rtw89_btc_rf_trx_para rf_trx_para; struct rtw89_btc_wl_tx_limit_para wl_tx_limit; struct rtw89_btc_dm_step dm_step; @@ -2539,6 +2606,18 @@ struct rtw89_btc_ctrl { u32 rsvd: 12; }; +struct rtw89_btc_ctrl_v7 { + u8 manual; + u8 igno_bt; + u8 always_freerun; + u8 rsvd; +} __packed; + +union rtw89_btc_ctrl_list { + struct rtw89_btc_ctrl ctrl; + struct rtw89_btc_ctrl_v7 ctrl_v7; +}; + struct rtw89_btc_dbg { /* cmd "rb" */ bool rb_done; @@ -2711,7 +2790,9 @@ struct rtw89_btc_ver { u8 fwlrole; u8 frptmap; u8 fcxctrl; + u8 fcxinit; + u8 drvinfo_type; u16 info_buf; u8 max_role_num; }; @@ -2723,8 +2804,8 @@ struct rtw89_btc { struct rtw89_btc_cx cx; struct rtw89_btc_dm dm; - struct rtw89_btc_ctrl ctrl; - struct rtw89_btc_module mdinfo; + union rtw89_btc_ctrl_list ctrl; + union rtw89_btc_module_info mdinfo; struct rtw89_btc_btf_fwinfo fwinfo; struct rtw89_btc_dbg dbg; @@ -2736,11 +2817,14 @@ struct rtw89_btc { u32 bt_req_len; u8 policy[RTW89_BTC_POLICY_MAXLEN]; + u8 ant_type; + u8 btg_pos; u16 policy_len; u16 policy_type; bool bt_req_en; bool update_policy_force; bool lps; + bool manual_ctrl; }; enum rtw89_btc_hmsg { @@ -3118,7 +3202,7 @@ struct rtw89_hci_ops { void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); - int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); + int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); void (*clr_idx_all)(struct rtw89_dev *rtwdev); void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); void (*disable_intr)(struct rtw89_dev *rtwdev); @@ -3870,6 +3954,7 @@ struct rtw89_chip_info { const u32 *c2h_regs; struct rtw89_reg_def c2h_counter_reg; const struct rtw89_page_regs *page_regs; + u32 wow_reason_reg; bool cfo_src_fd; bool cfo_hw_comp; const struct rtw89_reg_def *dcfo_comp; @@ -5168,12 +5253,12 @@ static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); } -static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) +static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) { int ret = 0; - if (rtwdev->hci.ops->poll_txdma_ch) - ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); + if (rtwdev->hci.ops->poll_txdma_ch_idle) + ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); return ret; } diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c index 44829a148185..affffc4092ba 100644 --- a/drivers/net/wireless/realtek/rtw89/debug.c +++ b/drivers/net/wireless/realtek/rtw89/debug.c @@ -3427,14 +3427,17 @@ static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; struct rtw89_btc *btc = &rtwdev->btc; - bool btc_manual; + const struct rtw89_btc_ver *ver = btc->ver; int ret; - ret = kstrtobool_from_user(user_buf, count, &btc_manual); + ret = kstrtobool_from_user(user_buf, count, &btc->manual_ctrl); if (ret) return ret; - btc->ctrl.manual = btc_manual; + if (ver->fcxctrl == 7) + btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; + else + btc->ctrl.ctrl.manual = btc->manual_ctrl; return count; } diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 63897351ca15..185cd339c085 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -3753,11 +3753,11 @@ fail: return ret; } -int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev) +int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_dm *dm = &btc->dm; - struct rtw89_btc_init_info *init_info = &dm->init_info; + struct rtw89_btc_init_info *init_info = &dm->init_info.init; struct rtw89_btc_module *module = &init_info->module; struct rtw89_btc_ant_info *ant = &module->ant; struct rtw89_h2c_cxinit *h2c; @@ -3773,7 +3773,7 @@ int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev) skb_put(skb, len); h2c = (struct rtw89_h2c_cxinit *)skb->data; - h2c->hdr.type = CXDRVINFO_INIT; + h2c->hdr.type = type; h2c->hdr.len = len - H2C_LEN_CXDRVHDR; h2c->ant_type = ant->type; @@ -3820,12 +3820,53 @@ fail: return ret; } +int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type) +{ + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_dm *dm = &btc->dm; + struct rtw89_btc_init_info_v7 *init_info = &dm->init_info.init_v7; + struct rtw89_h2c_cxinit_v7 *h2c; + u32 len = sizeof(*h2c); + struct sk_buff *skb; + int ret; + + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); + if (!skb) { + rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_init_v7\n"); + return -ENOMEM; + } + skb_put(skb, len); + h2c = (struct rtw89_h2c_cxinit_v7 *)skb->data; + + h2c->hdr.type = type; + h2c->hdr.ver = btc->ver->fcxinit; + h2c->hdr.len = len - H2C_LEN_CXDRVHDR_V7; + h2c->init = *init_info; + + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, + H2C_CAT_OUTSRC, BTFC_SET, + SET_DRV_INFO, 0, 0, + len); + + ret = rtw89_h2c_tx(rtwdev, skb, false); + if (ret) { + rtw89_err(rtwdev, "failed to send h2c\n"); + goto fail; + } + + return 0; +fail: + dev_kfree_skb_any(skb); + + return ret; +} + #define PORT_DATA_OFFSET 4 #define H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN 12 #define H2C_LEN_CXDRVINFO_ROLE_SIZE(max_role_num) \ (4 + 12 * (max_role_num) + H2C_LEN_CXDRVHDR) -int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev) +int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; const struct rtw89_btc_ver *ver = btc->ver; @@ -3850,7 +3891,7 @@ int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev) skb_put(skb, len); cmd = skb->data; - RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE); + RTW89_SET_FWCMD_CXHDR_TYPE(cmd, type); RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR); RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt); @@ -3906,7 +3947,7 @@ fail: #define H2C_LEN_CXDRVINFO_ROLE_SIZE_V1(max_role_num) \ (4 + 16 * (max_role_num) + H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN + H2C_LEN_CXDRVHDR) -int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev) +int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; const struct rtw89_btc_ver *ver = btc->ver; @@ -3930,7 +3971,7 @@ int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev) skb_put(skb, len); cmd = skb->data; - RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE); + RTW89_SET_FWCMD_CXHDR_TYPE(cmd, type); RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR); RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt); @@ -3996,7 +4037,7 @@ fail: #define H2C_LEN_CXDRVINFO_ROLE_SIZE_V2(max_role_num) \ (4 + 8 * (max_role_num) + H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN + H2C_LEN_CXDRVHDR) -int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev) +int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; const struct rtw89_btc_ver *ver = btc->ver; @@ -4020,7 +4061,7 @@ int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev) skb_put(skb, len); cmd = skb->data; - RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE); + RTW89_SET_FWCMD_CXHDR_TYPE(cmd, type); RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR); RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt); @@ -4080,11 +4121,11 @@ fail: } #define H2C_LEN_CXDRVINFO_CTRL (4 + H2C_LEN_CXDRVHDR) -int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev) +int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; const struct rtw89_btc_ver *ver = btc->ver; - struct rtw89_btc_ctrl *ctrl = &btc->ctrl; + struct rtw89_btc_ctrl *ctrl = &btc->ctrl.ctrl; struct sk_buff *skb; u8 *cmd; int ret; @@ -4097,7 +4138,7 @@ int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev) skb_put(skb, H2C_LEN_CXDRVINFO_CTRL); cmd = skb->data; - RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_CTRL); + RTW89_SET_FWCMD_CXHDR_TYPE(cmd, type); RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_CTRL - H2C_LEN_CXDRVHDR); RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, ctrl->manual); @@ -4124,8 +4165,47 @@ fail: return ret; } +int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type) +{ + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_ctrl_v7 *ctrl = &btc->ctrl.ctrl_v7; + struct rtw89_h2c_cxctrl_v7 *h2c; + u32 len = sizeof(*h2c); + struct sk_buff *skb; + int ret; + + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); + if (!skb) { + rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n"); + return -ENOMEM; + } + skb_put(skb, len); + h2c = (struct rtw89_h2c_cxctrl_v7 *)skb->data; + + h2c->hdr.type = type; + h2c->hdr.ver = btc->ver->fcxctrl; + h2c->hdr.len = sizeof(*h2c) - H2C_LEN_CXDRVHDR_V7; + h2c->ctrl = *ctrl; + + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, + H2C_CAT_OUTSRC, BTFC_SET, + SET_DRV_INFO, 0, 0, len); + + ret = rtw89_h2c_tx(rtwdev, skb, false); + if (ret) { + rtw89_err(rtwdev, "failed to send h2c\n"); + goto fail; + } + + return 0; +fail: + dev_kfree_skb_any(skb); + + return ret; +} + #define H2C_LEN_CXDRVINFO_TRX (28 + H2C_LEN_CXDRVHDR) -int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev) +int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_trx_info *trx = &btc->dm.trx_info; @@ -4141,7 +4221,7 @@ int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev) skb_put(skb, H2C_LEN_CXDRVINFO_TRX); cmd = skb->data; - RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_TRX); + RTW89_SET_FWCMD_CXHDR_TYPE(cmd, type); RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_TRX - H2C_LEN_CXDRVHDR); RTW89_SET_FWCMD_CXTRX_TXLV(cmd, trx->tx_lvl); @@ -4181,7 +4261,7 @@ fail: } #define H2C_LEN_CXDRVINFO_RFK (4 + H2C_LEN_CXDRVHDR) -int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev) +int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type) { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_wl_info *wl = &btc->cx.wl; @@ -4198,7 +4278,7 @@ int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev) skb_put(skb, H2C_LEN_CXDRVINFO_RFK); cmd = skb->data; - RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_RFK); + RTW89_SET_FWCMD_CXHDR_TYPE(cmd, type); RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_RFK - H2C_LEN_CXDRVHDR); RTW89_SET_FWCMD_CXRFK_STATE(cmd, rfk_info->state); @@ -5739,7 +5819,7 @@ int rtw89_hw_scan_add_chan_list(struct rtw89_dev *rtwdev, goto out; } - if (req->duration_mandatory) + if (req->duration) ch_info->period = req->duration; else if (channel->band == NL80211_BAND_6GHZ) ch_info->period = RTW89_CHANNEL_TIME_6G + @@ -5817,7 +5897,7 @@ int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev, goto out; } - if (req->duration_mandatory) + if (req->duration) ch_info->period = req->duration; else if (channel->band == NL80211_BAND_6GHZ) ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME_6G; diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 9c5464dcc081..44311f65b4fa 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -64,6 +64,8 @@ struct rtw89_h2creg_sch_tx_en { #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0) #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16) +#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16) + #define RTW89_H2CREG_MAX 4 #define RTW89_C2HREG_MAX 4 #define RTW89_C2HREG_HDR_LEN 2 @@ -95,7 +97,9 @@ enum rtw89_mac_h2c_type { RTW89_FWCMD_H2CREG_FUNC_FWERR, RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, - RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN + RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN, + RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP = 0x6, + RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL = 0xA, }; enum rtw89_mac_c2h_type { @@ -104,7 +108,8 @@ enum rtw89_mac_c2h_type { RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, - RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF + RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA, + RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF, }; enum rtw89_fw_c2h_category { @@ -2324,9 +2329,15 @@ enum rtw89_btc_btf_set { SET_BT_IGNORE_WLAN_ACT, SET_BT_TX_PWR, SET_BT_LNA_CONSTRAIN, - SET_BT_GOLDEN_RX_RANGE, + SET_BT_QUERY_DEV_LIST, + SET_BT_QUERY_DEV_INFO, SET_BT_PSD_REPORT, SET_H2C_TEST, + SET_IOFLD_RF, + SET_IOFLD_BB, + SET_IOFLD_MAC, + SET_IOFLD_SCBD, + SET_H2C_MACRO, SET_MAX1, }; @@ -2340,6 +2351,10 @@ enum rtw89_btc_cxdrvinfo { CXDRVINFO_CTRL, CXDRVINFO_SCAN, CXDRVINFO_TRX, /* WL traffic to WL fw */ + CXDRVINFO_TXPWR, + CXDRVINFO_FDDT, + CXDRVINFO_MLO, + CXDRVINFO_OSI, CXDRVINFO_MAX, }; @@ -2366,7 +2381,19 @@ struct rtw89_h2c_cxhdr { u8 len; } __packed; +struct rtw89_h2c_cxhdr_v7 { + u8 type; + u8 ver; + u8 len; +} __packed; + +struct rtw89_h2c_cxctrl_v7 { + struct rtw89_h2c_cxhdr_v7 hdr; + struct rtw89_btc_ctrl_v7 ctrl; +} __packed; + #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr) +#define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7) struct rtw89_h2c_cxinit { struct rtw89_h2c_cxhdr hdr; @@ -2400,6 +2427,11 @@ struct rtw89_h2c_cxinit { #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3) #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4) +struct rtw89_h2c_cxinit_v7 { + struct rtw89_h2c_cxhdr_v7 hdr; + struct rtw89_btc_init_info_v7 init; +} __packed; + static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) { u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); @@ -4531,13 +4563,15 @@ int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev, struct rtw89_rx_phy_ppdu *phy_ppdu); int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); -int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); -int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); -int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); -int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev); -int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); -int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev); -int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); +int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type); +int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, struct sk_buff *skb_ofld); diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c index 908245ac46bd..aa5b396b5d2b 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.c +++ b/drivers/net/wireless/realtek/rtw89/mac.c @@ -2025,6 +2025,9 @@ void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) { u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; + if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) + return; + if (enable) rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); else @@ -5615,7 +5618,8 @@ int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, } EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); -int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) +static +int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) { u32 reg; u16 val; @@ -5711,7 +5715,7 @@ bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) return !!val; } -u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) +static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) { u32 reg; u16 cnt; @@ -6265,6 +6269,41 @@ int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, return ret; } +static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + int ret; + + if (enable_wow) { + ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); + if (ret) { + rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); + return ret; + } + + rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); + rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); + rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); + rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); + rtw89_write32(rtwdev, R_AX_TF_FWD, 0); + rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); + } else { + ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); + if (ret) { + rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); + return ret; + } + + rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); + rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); + rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); + } + + return 0; +} + static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) { u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); @@ -6307,6 +6346,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { .addr = R_AX_RXTRIG_TEST_USER_2, .mask = B_AX_RXTRIG_RU26_DIS, }, + .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, .check_mac_en = rtw89_mac_check_mac_en_ax, .sys_init = sys_init_ax, @@ -6340,6 +6380,9 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { .parse_phycap_map = rtw89_parse_phycap_map_ax, .cnv_efuse_state = rtw89_cnv_efuse_state_ax, + .cfg_plt = rtw89_mac_cfg_plt_ax, + .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, + .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, .write_xtal_si = rtw89_mac_write_xtal_si_ax, @@ -6352,5 +6395,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { .add_chan_list = rtw89_hw_scan_add_chan_list, .scan_offload = rtw89_fw_h2c_scan_offload, + + .wow_config_mac = rtw89_wow_config_mac_ax, }; EXPORT_SYMBOL(rtw89_mac_gen_ax); diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h index db95509fad2f..6fb457153a11 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.h +++ b/drivers/net/wireless/realtek/rtw89/mac.h @@ -169,6 +169,12 @@ enum rtw89_mac_ax_l0_to_l1_event { MAC_AX_L0_TO_L1_EVENT_MAX = 15, }; +enum rtw89_mac_wow_fw_status { + WOWLAN_NOT_READY = 0x00, + WOWLAN_SLEEP_READY = 0x01, + WOWLAN_RESUME_READY = 0x02, +}; + #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) enum rtw89_mac_dbg_port_sel { @@ -913,6 +919,7 @@ struct rtw89_mac_gen_def { struct rtw89_reg_def muedca_ctrl; struct rtw89_reg_def bfee_ctrl; struct rtw89_reg_def narrow_bw_ru_dis; + struct rtw89_reg_def wow_ctrl; int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, enum rtw89_mac_hwmod_sel sel); @@ -958,6 +965,9 @@ struct rtw89_mac_gen_def { int (*parse_phycap_map)(struct rtw89_dev *rtwdev); int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); + int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); + u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band); + bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u32 reg_base, u32 *cr); @@ -976,6 +986,8 @@ struct rtw89_mac_gen_def { int (*scan_offload)(struct rtw89_dev *rtwdev, struct rtw89_scan_option *option, struct rtw89_vif *rtwvif); + + int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow); }; extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; @@ -1185,13 +1197,31 @@ int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg); int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg); -int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); -u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); +int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, + const struct rtw89_mac_ax_coex_gnt *gnt_cfg); + +static inline +int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->cfg_plt(rtwdev, plt); +} + +static inline +u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + return mac->get_plt_cnt(rtwdev, band); +} + void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); +int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c index 320e88229971..f16467377eab 100644 --- a/drivers/net/wireless/realtek/rtw89/mac_be.c +++ b/drivers/net/wireless/realtek/rtw89/mac_be.c @@ -1797,6 +1797,120 @@ static int trx_init_be(struct rtw89_dev *rtwdev) return 0; } +int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, + const struct rtw89_mac_ax_coex_gnt *gnt_cfg) +{ + u32 val = 0; + + if (gnt_cfg->band[0].gnt_bt) + val |= B_BE_GNT_BT_BB0_VAL | B_BE_GNT_BT_RX_BB0_VAL | + B_BE_GNT_BT_TX_BB0_VAL; + + if (gnt_cfg->band[0].gnt_bt_sw_en) + val |= B_BE_GNT_BT_BB0_SWCTRL | B_BE_GNT_BT_RX_BB0_SWCTRL | + B_BE_GNT_BT_TX_BB0_SWCTRL; + + if (gnt_cfg->band[0].gnt_wl) + val |= B_BE_GNT_WL_BB0_VAL | B_BE_GNT_WL_RX_VAL | + B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL; + + if (gnt_cfg->band[0].gnt_wl_sw_en) + val |= B_BE_GNT_WL_BB0_SWCTRL | B_BE_GNT_WL_RX_SWCTRL | + B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL; + + if (gnt_cfg->band[1].gnt_bt) + val |= B_BE_GNT_BT_BB1_VAL | B_BE_GNT_BT_RX_BB1_VAL | + B_BE_GNT_BT_TX_BB1_VAL; + + if (gnt_cfg->band[1].gnt_bt_sw_en) + val |= B_BE_GNT_BT_BB1_SWCTRL | B_BE_GNT_BT_RX_BB1_SWCTRL | + B_BE_GNT_BT_TX_BB1_SWCTRL; + + if (gnt_cfg->band[1].gnt_wl) + val |= B_BE_GNT_WL_BB1_VAL | B_BE_GNT_WL_RX_VAL | + B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL; + + if (gnt_cfg->band[1].gnt_wl_sw_en) + val |= B_BE_GNT_WL_BB1_SWCTRL | B_BE_GNT_WL_RX_SWCTRL | + B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL; + + if (gnt_cfg->bt[0].wlan_act_en) + val |= B_BE_WL_ACT_SWCTRL; + if (gnt_cfg->bt[0].wlan_act) + val |= B_BE_WL_ACT_VAL; + if (gnt_cfg->bt[1].wlan_act_en) + val |= B_BE_WL_ACT2_SWCTRL; + if (gnt_cfg->bt[1].wlan_act) + val |= B_BE_WL_ACT2_VAL; + + rtw89_write32(rtwdev, R_BE_GNT_SW_CTRL, val); + + return 0; +} +EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v2); + +int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl) +{ + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_dm *dm = &btc->dm; + struct rtw89_mac_ax_gnt *g = dm->gnt.band; + struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt; + int i; + + if (wl) + return 0; + + for (i = 0; i < RTW89_PHY_MAX; i++) { + g[i].gnt_bt_sw_en = 1; + g[i].gnt_bt = 1; + g[i].gnt_wl_sw_en = 1; + g[i].gnt_wl = 0; + gbt[i].wlan_act = 1; + gbt[i].wlan_act_en = 0; + } + + return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt); +} +EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v2); + +static +int rtw89_mac_cfg_plt_be(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) +{ + u32 reg; + u16 val; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band); + val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) | + (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) | + (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) | + (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) | + (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) | + (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) | + (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) | + (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) | + B_BE_PLT_EN; + rtw89_write16(rtwdev, reg, val); + + return 0; +} + +static u16 rtw89_mac_get_plt_cnt_be(struct rtw89_dev *rtwdev, u8 band) +{ + u32 reg; + u16 cnt; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, band); + cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK); + rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST); + + return cnt; +} + static int rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en, u32 tx_en_mask) { @@ -2193,6 +2307,52 @@ static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev) dump_err_status_dispatcher_be(rtwdev); } +static int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) +{ + struct rtw89_mac_h2c_info h2c_info = {}; + struct rtw89_mac_c2h_info c2h_info = {}; + u32 ret; + + h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; + h2c_info.content_len = sizeof(h2c_info.u.hdr); + h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); + + ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); + if (ret) + return ret; + + if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) + ret = -EINVAL; + + return ret; +} + +static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow) +{ + if (enable_wow) { + rtw89_write32_set(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP); + rtw89_write32_clr(rtwdev, R_BE_RX_FLTR_OPT, B_BE_SNIFFER_MODE); + rtw89_mac_cpu_io_rx(rtwdev, enable_wow); + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); + rtw89_write32(rtwdev, R_BE_FWD_ERR, 0); + rtw89_write32(rtwdev, R_BE_FWD_ACTN0, 0); + rtw89_write32(rtwdev, R_BE_FWD_ACTN1, 0); + rtw89_write32(rtwdev, R_BE_FWD_ACTN2, 0); + rtw89_write32(rtwdev, R_BE_FWD_TF0, 0); + rtw89_write32(rtwdev, R_BE_FWD_TF1, 0); + rtw89_write32(rtwdev, R_BE_FWD_ERR, 0); + rtw89_write32(rtwdev, R_BE_HW_PPDU_STATUS, 0); + rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); + } else { + rtw89_mac_cpu_io_rx(rtwdev, enable_wow); + rtw89_write32_clr(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP); + rtw89_write32_set(rtwdev, R_BE_RX_FLTR_OPT, R_BE_RX_FLTR_OPT); + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); + } + + return 0; +} + static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev, u8 band) { @@ -2406,6 +2566,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .addr = R_BE_RXTRIG_TEST_USER_2, .mask = B_BE_RXTRIG_RU26_DIS, }, + .wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,}, .check_mac_en = rtw89_mac_check_mac_en_be, .sys_init = sys_init_be, @@ -2439,6 +2600,9 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .parse_phycap_map = rtw89_parse_phycap_map_be, .cnv_efuse_state = rtw89_cnv_efuse_state_be, + .cfg_plt = rtw89_mac_cfg_plt_be, + .get_plt_cnt = rtw89_mac_get_plt_cnt_be, + .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be, .write_xtal_si = rtw89_mac_write_xtal_si_be, @@ -2451,5 +2615,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .add_chan_list = rtw89_hw_scan_add_chan_list_be, .scan_offload = rtw89_fw_h2c_scan_offload_be, + + .wow_config_mac = rtw89_wow_config_mac_be, }; EXPORT_SYMBOL(rtw89_mac_gen_be); diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c index 67d7294e488a..19001130ad94 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.c +++ b/drivers/net/wireless/realtek/rtw89/pci.c @@ -218,7 +218,7 @@ int rtw89_pci_sync_skb_for_device_and_validate_rx_info(struct rtw89_dev *rtwdev, return ret; } -static void rtw89_pci_ctrl_txdma_ch_pcie(struct rtw89_dev *rtwdev, bool enable) +static void rtw89_pci_ctrl_txdma_ch_ax(struct rtw89_dev *rtwdev, bool enable) { const struct rtw89_pci_info *info = rtwdev->pci_info; const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; @@ -235,7 +235,7 @@ static void rtw89_pci_ctrl_txdma_ch_pcie(struct rtw89_dev *rtwdev, bool enable) } } -static void rtw89_pci_ctrl_txdma_fw_ch_pcie(struct rtw89_dev *rtwdev, bool enable) +static void rtw89_pci_ctrl_txdma_fw_ch_ax(struct rtw89_dev *rtwdev, bool enable) { const struct rtw89_pci_info *info = rtwdev->pci_info; const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; @@ -2524,7 +2524,7 @@ static void rtw89_pci_clr_idx_all_ax(struct rtw89_dev *rtwdev) B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX); } -static int rtw89_poll_txdma_ch_idle_pcie(struct rtw89_dev *rtwdev) +static int rtw89_pci_poll_txdma_ch_idle_ax(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; u32 ret, check, dma_busy; @@ -2551,7 +2551,7 @@ static int rtw89_poll_txdma_ch_idle_pcie(struct rtw89_dev *rtwdev) return 0; } -static int rtw89_poll_rxdma_ch_idle_pcie(struct rtw89_dev *rtwdev) +static int rtw89_pci_poll_rxdma_ch_idle_ax(struct rtw89_dev *rtwdev) { const struct rtw89_pci_info *info = rtwdev->pci_info; u32 ret, check, dma_busy; @@ -2571,13 +2571,13 @@ static int rtw89_pci_poll_dma_all_idle(struct rtw89_dev *rtwdev) { u32 ret; - ret = rtw89_poll_txdma_ch_idle_pcie(rtwdev); + ret = rtw89_pci_poll_txdma_ch_idle_ax(rtwdev); if (ret) { rtw89_err(rtwdev, "txdma ch busy\n"); return ret; } - ret = rtw89_poll_rxdma_ch_idle_pcie(rtwdev); + ret = rtw89_pci_poll_rxdma_ch_idle_ax(rtwdev); if (ret) { rtw89_err(rtwdev, "rxdma ch busy\n"); return ret; @@ -2756,8 +2756,8 @@ static int rtw89_pci_ops_mac_pre_init_ax(struct rtw89_dev *rtwdev) } /* disable all channels except to FW CMD channel to download firmware */ - rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, false); - rtw89_pci_ctrl_txdma_fw_ch_pcie(rtwdev, true); + rtw89_pci_ctrl_txdma_ch_ax(rtwdev, false); + rtw89_pci_ctrl_txdma_fw_ch_ax(rtwdev, true); /* start DMA activities */ rtw89_pci_ctrl_dma_all(rtwdev, true); @@ -2870,7 +2870,7 @@ static int rtw89_pci_ops_mac_post_init_ax(struct rtw89_dev *rtwdev) } /* enable DMA for all queues */ - rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, true); + rtw89_pci_ctrl_txdma_ch_ax(rtwdev, true); /* Release PCI IO */ rtw89_write32_clr(rtwdev, info->dma_stop1.addr, @@ -3652,12 +3652,20 @@ static int rtw89_pci_filter_out(struct rtw89_dev *rtwdev) static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) { - enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; - int ret; + const struct rtw89_pci_info *info = rtwdev->pci_info; + const struct rtw89_pci_gen_def *gen_def = info->gen_def; if (rtw89_pci_disable_clkreq) return; + gen_def->clkreq_set(rtwdev, enable); +} + +static void rtw89_pci_clkreq_set_ax(struct rtw89_dev *rtwdev, bool enable) +{ + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; + int ret; + ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, PCIE_CLKDLY_HW_30US); if (ret) @@ -3689,24 +3697,31 @@ static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable) { - enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; - u8 value = 0; - int ret; + const struct rtw89_pci_info *info = rtwdev->pci_info; + const struct rtw89_pci_gen_def *gen_def = info->gen_def; if (rtw89_pci_disable_aspm_l1) return; + gen_def->aspm_set(rtwdev, enable); +} + +static void rtw89_pci_aspm_set_ax(struct rtw89_dev *rtwdev, bool enable) +{ + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; + u8 value = 0; + int ret; + ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, &value); if (ret) - rtw89_err(rtwdev, "failed to read ASPM Delay\n"); + rtw89_warn(rtwdev, "failed to read ASPM Delay\n"); - value &= ~(RTW89_L1DLY_MASK | RTW89_L0DLY_MASK); - value |= FIELD_PREP(RTW89_L1DLY_MASK, PCIE_L1DLY_16US) | - FIELD_PREP(RTW89_L0DLY_MASK, PCIE_L0SDLY_4US); + u8p_replace_bits(&value, PCIE_L1DLY_16US, RTW89_L1DLY_MASK); + u8p_replace_bits(&value, PCIE_L0SDLY_4US, RTW89_L0DLY_MASK); ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, value); if (ret) - rtw89_err(rtwdev, "failed to read ASPM Delay\n"); + rtw89_warn(rtwdev, "failed to read ASPM Delay\n"); if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) { if (enable) @@ -3793,6 +3808,17 @@ static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev) static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable) { + const struct rtw89_pci_info *info = rtwdev->pci_info; + const struct rtw89_pci_gen_def *gen_def = info->gen_def; + + if (rtw89_pci_disable_l1ss) + return; + + gen_def->l1ss_set(rtwdev, enable); +} + +static void rtw89_pci_l1ss_set_ax(struct rtw89_dev *rtwdev, bool enable) +{ enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; int ret; @@ -4066,6 +4092,14 @@ const struct rtw89_pci_gen_def rtw89_pci_gen_ax = { .lv1rst_stop_dma = rtw89_pci_lv1rst_stop_dma_ax, .lv1rst_start_dma = rtw89_pci_lv1rst_start_dma_ax, + + .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_ax, + .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_ax, + .poll_txdma_ch_idle = rtw89_pci_poll_txdma_ch_idle_ax, + + .aspm_set = rtw89_pci_aspm_set_ax, + .clkreq_set = rtw89_pci_clkreq_set_ax, + .l1ss_set = rtw89_pci_l1ss_set_ax, }; EXPORT_SYMBOL(rtw89_pci_gen_ax); @@ -4100,10 +4134,11 @@ static const struct rtw89_hci_ops rtw89_pci_ops = { .recovery_start = rtw89_pci_ops_recovery_start, .recovery_complete = rtw89_pci_ops_recovery_complete, - .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_pcie, - .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_pcie, + .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch, + .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch, .ctrl_trxhci = rtw89_pci_ctrl_dma_trx, - .poll_txdma_ch = rtw89_poll_txdma_ch_idle_pcie, + .poll_txdma_ch_idle = rtw89_pci_poll_txdma_ch_idle, + .clr_idx_all = rtw89_pci_clr_idx_all, .clear = rtw89_pci_clear_resource, .disable_intr = rtw89_pci_disable_intr_lock, diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h index 532f78eaf6df..a63b6b7c9bfa 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.h +++ b/drivers/net/wireless/realtek/rtw89/pci.h @@ -282,6 +282,21 @@ #define B_BE_PCIE_EN_SWENT_L23 BIT(1) #define B_BE_SEL_REQ_EXIT_L1 BIT(0) +#define R_BE_PCIE_MIX_CFG 0x300C +#define B_BE_L1SS_TIMEOUT_CTRL BIT(18) +#define B_BE_ASPM_CTRL_L1 BIT(17) +#define B_BE_ASPM_CTRL_L0 BIT(16) +#define B_BE_XFER_PENDING_FW BIT(11) +#define B_BE_XFER_PENDING BIT(10) +#define B_BE_REQ_EXIT_L1 BIT(9) +#define B_BE_REQ_ENTR_L1 BIT(8) +#define B_BE_L1SUB_ENABLE BIT(0) + +#define R_BE_L1_CLK_CTRL 0x3010 +#define B_BE_RAS_SD_HOLD_LTSSM BIT(12) +#define B_BE_CLK_REQ_N BIT(1) +#define B_BE_CLK_PM_EN BIT(0) + #define R_BE_PCIE_LAT_CTRL 0x3044 #define B_BE_ELBI_PHY_REMAP_MASK GENMASK(29, 24) #define B_BE_SYS_SUS_L12_EN BIT(17) @@ -290,6 +305,8 @@ #define B_BE_RTK_LDO_POWER_LATENCY_MASK GENMASK(11, 10) #define B_BE_RTK_LDO_BIAS_LATENCY_MASK GENMASK(9, 8) #define B_BE_CLK_REQ_LAT_MASK GENMASK(7, 4) +#define B_BE_RTK_PM_SEL_OPT BIT(1) +#define B_BE_CLK_REQ_SEL BIT(0) #define R_BE_PCIE_HIMR0 0x30B0 #define B_BE_PCIE_HB1_IND_INTA_IMR BIT(31) @@ -925,6 +942,8 @@ #define B_BE_SER_L1SUB_IMR BIT(1) #define B_BE_SER_PMU_IMR BIT(0) +#define R_BE_REG_PL1_ISR 0x34B4 + #define R_BE_RX_APPEND_MODE 0x8920 #define B_BE_APPEND_OFFSET_MASK GENMASK(23, 16) #define B_BE_APPEND_LEN_MASK GENMASK(15, 0) @@ -1066,6 +1085,15 @@ enum rtw89_pcie_clkdly_hw { PCIE_CLKDLY_HW_200US = 0x5, }; +enum rtw89_pcie_clkdly_hw_v1 { + PCIE_CLKDLY_HW_V1_0 = 0, + PCIE_CLKDLY_HW_V1_16US = 0x1, + PCIE_CLKDLY_HW_V1_32US = 0x2, + PCIE_CLKDLY_HW_V1_64US = 0x3, + PCIE_CLKDLY_HW_V1_80US = 0x4, + PCIE_CLKDLY_HW_V1_96US = 0x5, +}; + enum mac_ax_bd_trunc_mode { MAC_AX_BD_NORM, MAC_AX_BD_TRUNC, @@ -1216,6 +1244,14 @@ struct rtw89_pci_gen_def { int (*lv1rst_stop_dma)(struct rtw89_dev *rtwdev); int (*lv1rst_start_dma)(struct rtw89_dev *rtwdev); + + void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); + void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); + int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); + + void (*aspm_set)(struct rtw89_dev *rtwdev, bool enable); + void (*clkreq_set)(struct rtw89_dev *rtwdev, bool enable); + void (*l1ss_set)(struct rtw89_dev *rtwdev, bool enable); }; struct rtw89_pci_info { @@ -1524,6 +1560,7 @@ static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val) } extern const struct dev_pm_ops rtw89_pm_ops; +extern const struct dev_pm_ops rtw89_pm_ops_be; extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set; extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1; extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be; @@ -1679,4 +1716,27 @@ static inline int rtw89_pci_reset_bdram(struct rtw89_dev *rtwdev) return gen_def->rst_bdram(rtwdev); } +static inline void rtw89_pci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) +{ + const struct rtw89_pci_info *info = rtwdev->pci_info; + const struct rtw89_pci_gen_def *gen_def = info->gen_def; + + return gen_def->ctrl_txdma_ch(rtwdev, enable); +} + +static inline void rtw89_pci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) +{ + const struct rtw89_pci_info *info = rtwdev->pci_info; + const struct rtw89_pci_gen_def *gen_def = info->gen_def; + + return gen_def->ctrl_txdma_fw_ch(rtwdev, enable); +} + +static inline int rtw89_pci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) +{ + const struct rtw89_pci_info *info = rtwdev->pci_info; + const struct rtw89_pci_gen_def *gen_def = info->gen_def; + + return gen_def->poll_txdma_ch_idle(rtwdev); +} #endif diff --git a/drivers/net/wireless/realtek/rtw89/pci_be.c b/drivers/net/wireless/realtek/rtw89/pci_be.c index 5c9e39357773..7cc328222965 100644 --- a/drivers/net/wireless/realtek/rtw89/pci_be.c +++ b/drivers/net/wireless/realtek/rtw89/pci_be.c @@ -19,6 +19,54 @@ enum pcie_rxbd_mode { #define PL0_TMR_MAC_1MS 0x27100 #define PL0_TMR_AUX_1MS 0x1E848 +static void rtw89_pci_aspm_set_be(struct rtw89_dev *rtwdev, bool enable) +{ + struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; + struct pci_dev *pdev = rtwpci->pdev; + u8 value = 0; + int ret; + + ret = pci_read_config_byte(pdev, RTW89_PCIE_ASPM_CTRL, &value); + if (ret) + rtw89_warn(rtwdev, "failed to read ASPM Delay\n"); + + u8p_replace_bits(&value, PCIE_L1DLY_16US, RTW89_L1DLY_MASK); + + ret = pci_write_config_byte(pdev, RTW89_PCIE_ASPM_CTRL, value); + if (ret) + rtw89_warn(rtwdev, "failed to write ASPM Delay\n"); + + if (enable) + rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, + B_BE_ASPM_CTRL_L1); + else + rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, + B_BE_ASPM_CTRL_L1); +} + +static void rtw89_pci_l1ss_set_be(struct rtw89_dev *rtwdev, bool enable) +{ + if (enable) + rtw89_write32_set(rtwdev, R_BE_PCIE_MIX_CFG, + B_BE_L1SUB_ENABLE); + else + rtw89_write32_clr(rtwdev, R_BE_PCIE_MIX_CFG, + B_BE_L1SUB_ENABLE); +} + +static void rtw89_pci_clkreq_set_be(struct rtw89_dev *rtwdev, bool enable) +{ + rtw89_write32_mask(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_CLK_REQ_LAT_MASK, + PCIE_CLKDLY_HW_V1_0); + + if (enable) + rtw89_write32_set(rtwdev, R_BE_L1_CLK_CTRL, + B_BE_CLK_PM_EN); + else + rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL, + B_BE_CLK_PM_EN); +} + static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up) { if (power_up) @@ -269,8 +317,7 @@ static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev) rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32); } -static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool all_en, - bool h2c_en) +static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool enable) { u32 mask_all; u32 val; @@ -283,12 +330,19 @@ static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool all_en, val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1); val |= B_BE_STOP_CH13 | B_BE_STOP_CH14; - if (all_en) + if (enable) val &= ~mask_all; else val |= mask_all; - if (h2c_en) + rtw89_write32(rtwdev, R_BE_HAXI_DMA_STOP1, val); +} + +static void rtw89_pci_ctrl_txdma_fw_ch_be(struct rtw89_dev *rtwdev, bool enable) +{ + u32 val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1); + + if (enable) val &= ~B_BE_STOP_CH12; else val |= B_BE_STOP_CH12; @@ -327,7 +381,8 @@ static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev) rtw89_pci_pcie_setting_be(rtwdev); rtw89_pci_ser_setting_be(rtwdev); - rtw89_pci_ctrl_txdma_ch_be(rtwdev, false, true); + rtw89_pci_ctrl_txdma_ch_be(rtwdev, false); + rtw89_pci_ctrl_txdma_fw_ch_be(rtwdev, true); rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_ENABLE, MAC_AX_PCIE_ENABLE, MAC_AX_PCIE_ENABLE); @@ -437,7 +492,8 @@ static int rtw89_pci_ops_mac_post_init_be(struct rtw89_dev *rtwdev) rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_IGNORE, MAC_AX_PCIE_IGNORE, MAC_AX_PCIE_ENABLE); rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, true); - rtw89_pci_ctrl_txdma_ch_be(rtwdev, true, true); + rtw89_pci_ctrl_txdma_ch_be(rtwdev, true); + rtw89_pci_ctrl_txdma_fw_ch_be(rtwdev, true); rtw89_pci_configure_mit_be(rtwdev); return 0; @@ -494,6 +550,46 @@ static int rtw89_pci_lv1rst_start_dma_be(struct rtw89_dev *rtwdev) return 0; } +static int __maybe_unused rtw89_pci_suspend_be(struct device *dev) +{ + struct ieee80211_hw *hw = dev_get_drvdata(dev); + struct rtw89_dev *rtwdev = hw->priv; + + rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); + rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST); + rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); + rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST); + rtw89_write32_clr(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR); + return 0; +} + +static int __maybe_unused rtw89_pci_resume_be(struct device *dev) +{ + struct ieee80211_hw *hw = dev_get_drvdata(dev); + struct rtw89_dev *rtwdev = hw->priv; + u32 polling; + int ret; + + rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); + rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST); + rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); + rtw89_write32_clr(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST); + rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); + + ret = read_poll_timeout_atomic(rtw89_read32, polling, !polling, 1, 1000, + false, rtwdev, R_BE_REG_PL1_ISR); + if (ret) + rtw89_warn(rtwdev, "[ERR] PCIE SER clear polling fail\n"); + + rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); + rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR); + + return 0; +} + +SIMPLE_DEV_PM_OPS(rtw89_pm_ops_be, rtw89_pci_suspend_be, rtw89_pci_resume_be); +EXPORT_SYMBOL(rtw89_pm_ops_be); + const struct rtw89_pci_gen_def rtw89_pci_gen_be = { .isr_rdu = B_BE_RDU_CH1_INT | B_BE_RDU_CH0_INT, .isr_halt_c2h = B_BE_HALT_C2H_INT, @@ -510,5 +606,13 @@ const struct rtw89_pci_gen_def rtw89_pci_gen_be = { .lv1rst_stop_dma = rtw89_pci_lv1rst_stop_dma_be, .lv1rst_start_dma = rtw89_pci_lv1rst_start_dma_be, + + .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_be, + .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_be, + .poll_txdma_ch_idle = rtw89_pci_poll_txdma_ch_idle_be, + + .aspm_set = rtw89_pci_aspm_set_be, + .clkreq_set = rtw89_pci_clkreq_set_be, + .l1ss_set = rtw89_pci_l1ss_set_be, }; EXPORT_SYMBOL(rtw89_pci_gen_be); diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 37ccd8ffa87a..72e448e91b6f 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -3510,8 +3510,13 @@ #define B_AX_PTA_EDCCA_EN BIT(0) #define R_BTC_COEX_WL_REQ 0xDA24 +#define R_BTC_COEX_WL_REQ_BE 0xE324 +#define B_BTC_TX_NULL_HI BIT(23) #define B_BTC_TX_BCN_HI BIT(22) +#define B_BTC_TX_TRI_HI BIT(17) #define B_BTC_RSP_ACK_HI BIT(10) +#define B_BTC_PRI_MASK_TX_TIME GENMASK(4, 3) +#define B_BTC_PRI_MASK_RX_TIME_V1 GENMASK(2, 1) #define R_BTC_BREAK_TABLE 0xDA2C #define BTC_BREAK_PARAM 0xf0ffffff @@ -3759,6 +3764,19 @@ #define B_BE_SYM_PADPDN_WL_RFC1_1P3 BIT(6) #define B_BE_SYM_PADPDN_WL_RFC0_1P3 BIT(5) +#define R_BE_RSV_CTRL 0x001C +#define B_BE_HR_BE_DBG GENMASK(23, 12) +#define B_BE_R_SYM_DIS_PCIE_FLR BIT(9) +#define B_BE_R_EN_HRST_PWRON BIT(8) +#define B_BE_LOCK_ALL_EN BIT(7) +#define B_BE_R_DIS_PRST BIT(6) +#define B_BE_WLOCK_1C_BIT6 BIT(5) +#define B_BE_WLOCK_40 BIT(4) +#define B_BE_WLOCK_08 BIT(3) +#define B_BE_WLOCK_04 BIT(2) +#define B_BE_WLOCK_00 BIT(1) +#define B_BE_WLOCK_ALL BIT(0) + #define R_BE_AFE_LDO_CTRL 0x0020 #define B_BE_FORCE_MACBBBT_PWR_ON BIT(31) #define B_BE_R_SYM_WLPOFF_P4_PC_EN BIT(28) @@ -4451,6 +4469,9 @@ #define B_BE_HCI_RXDMA_EN BIT(1) #define B_BE_HCI_TXDMA_EN BIT(0) +#define R_BE_DBG_WOW_READY 0x815E +#define B_BE_DBG_WOW_READY GENMASK(7, 0) + #define R_BE_DMAC_FUNC_EN 0x8400 #define B_BE_DMAC_CRPRT BIT(31) #define B_BE_MAC_FUNC_EN BIT(30) @@ -5004,6 +5025,12 @@ B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \ B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN) +#define R_BE_RX_STOP 0x8914 +#define B_BE_CPU_RX_STOP BIT(17) +#define B_BE_HOST_RX_STOP BIT(16) +#define B_BE_CPU_RX_CH_STOP_MSK GENMASK(15, 8) +#define B_BE_HOST_RX_CH_STOP_MSK GENMASK(5, 0) + #define R_BE_DISP_FWD_WLAN_0 0x8938 #define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30) #define B_BE_FWD_WLAN_CPU_TYPE_12_MASK GENMASK(29, 28) @@ -5519,6 +5546,13 @@ #define B_BE_DROP_NONDMA_PPDU BIT(2) #define B_BE_APPEND_FCS BIT(0) +#define R_BE_FWD_ERR 0x9C10 +#define R_BE_FWD_ACTN0 0x9C14 +#define R_BE_FWD_ACTN1 0x9C18 +#define R_BE_FWD_ACTN2 0x9C1C +#define R_BE_FWD_TF0 0x9C20 +#define R_BE_FWD_TF1 0x9C24 + #define R_BE_HW_PPDU_STATUS 0x9C30 #define B_BE_FWD_RPKTTYPE_MASK GENMASK(31, 26) #define B_BE_FWD_PPDU_PRTID_MASK GENMASK(25, 23) @@ -5535,6 +5569,12 @@ #define B_BE_CUT_AMSDU_CHKLEN_L_TH_MASK GENMASK(23, 16) #define B_BE_CUT_AMSDU_CHKLEN_H_TH_MASK GENMASK(15, 0) +#define R_BE_WOW_CTRL 0x9CB8 +#define B_BE_WOW_HCI BIT(5) +#define B_BE_WOW_DROP BIT(2) +#define B_BE_WOW_WOWEN BIT(1) +#define B_BE_WOW_FORCE_WAKEUP BIT(0) + #define R_BE_RX_HDRTRNS 0x9CC0 #define B_BE_RX_MGN_MLD_ADDR_EN BIT(6) #define B_BE_HDR_INFO_MASK GENMASK(5, 4) @@ -5932,6 +5972,36 @@ #define B_BE_MACID_ACQ_GRP0_CLR_P BIT(2) #define B_BE_R_MACID_ACQ_CHK_EN BIT(0) +#define R_BE_BT_BREAK_TABLE 0x0E344 + +#define R_BE_GNT_SW_CTRL 0x0E348 +#define B_BE_WL_ACT2_VAL BIT(25) +#define B_BE_WL_ACT2_SWCTRL BIT(24) +#define B_BE_WL_ACT_VAL BIT(23) +#define B_BE_WL_ACT_SWCTRL BIT(22) +#define B_BE_GNT_BT_RX_BB1_VAL BIT(21) +#define B_BE_GNT_BT_RX_BB1_SWCTRL BIT(20) +#define B_BE_GNT_BT_TX_BB1_VAL BIT(19) +#define B_BE_GNT_BT_TX_BB1_SWCTRL BIT(18) +#define B_BE_GNT_BT_RX_BB0_VAL BIT(17) +#define B_BE_GNT_BT_RX_BB0_SWCTRL BIT(16) +#define B_BE_GNT_BT_TX_BB0_VAL BIT(15) +#define B_BE_GNT_BT_TX_BB0_SWCTRL BIT(14) +#define B_BE_GNT_WL_RX_VAL BIT(13) +#define B_BE_GNT_WL_RX_SWCTRL BIT(12) +#define B_BE_GNT_WL_TX_VAL BIT(11) +#define B_BE_GNT_WL_TX_SWCTRL BIT(10) +#define B_BE_GNT_BT_BB1_VAL BIT(9) +#define B_BE_GNT_BT_BB1_SWCTRL BIT(8) +#define B_BE_GNT_WL_BB1_VAL BIT(7) +#define B_BE_GNT_WL_BB1_SWCTRL BIT(6) +#define B_BE_GNT_BT_BB0_VAL BIT(5) +#define B_BE_GNT_BT_BB0_SWCTRL BIT(4) +#define B_BE_GNT_WL_BB0_VAL BIT(3) +#define B_BE_GNT_WL_BB0_SWCTRL BIT(2) +#define B_BE_GNT_WL_BB_PWR_VAL BIT(1) +#define B_BE_GNT_WL_BB_PWR_SWCTRL BIT(0) + #define R_BE_PWR_MACID_PATH_BASE 0x0E500 #define R_BE_PWR_MACID_LMT_BASE 0x0ED00 @@ -6457,6 +6527,20 @@ #define B_BE_PORT_DROP_4_0_MASK GENMASK(20, 16) #define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0) +#define R_BE_BT_PLT 0x1087C +#define R_BE_BT_PLT_C1 0x1487C +#define B_BE_BT_PLT_PKT_CNT_MASK GENMASK(31, 16) +#define B_BE_BT_PLT_RST BIT(9) +#define B_BE_PLT_EN BIT(8) +#define B_BE_RX_PLT_GNT_LTE_RX BIT(7) +#define B_BE_RX_PLT_GNT_BT_RX BIT(6) +#define B_BE_RX_PLT_GNT_BT_TX BIT(5) +#define B_BE_RX_PLT_GNT_WL BIT(4) +#define B_BE_TX_PLT_GNT_LTE_RX BIT(3) +#define B_BE_TX_PLT_GNT_BT_RX BIT(2) +#define B_BE_TX_PLT_GNT_BT_TX BIT(1) +#define B_BE_TX_PLT_GNT_WL BIT(0) + #define R_BE_PTCL_BSS_COLOR_0 0x108A0 #define R_BE_PTCL_BSS_COLOR_0_C1 0x148A0 #define B_BE_BSS_COLOB_BE_PORT_3_MASK GENMASK(29, 24) diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b.c b/drivers/net/wireless/realtek/rtw89/rtw8851b.c index 83db0a686ee2..51d3e61eaa1d 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8851b.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8851b.c @@ -1921,41 +1921,81 @@ static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev) { - struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; - - module->rfe_type = rtwdev->efuse.rfe_type; - module->cv = rtwdev->hal.cv; - module->bt_solo = 0; - module->switch_type = BTC_SWITCH_INTERNAL; - module->ant.isolation = 10; - module->kt_ver_adie = rtwdev->hal.acv; - - if (module->rfe_type == 0) - return; - - /* rfe_type 3*n+1: 1-Ant(shared), - * 3*n+2: 2-Ant+Div(non-shared), - * 3*n+3: 2-Ant+no-Div(non-shared) - */ - module->ant.num = (module->rfe_type % 3 == 1) ? 1 : 2; - /* WL-1ss at S0, btg at s0 (On 1 WL RF) */ - module->ant.single_pos = RF_PATH_A; - module->ant.btg_pos = RF_PATH_A; - module->ant.stream_cnt = 1; - - if (module->ant.num == 1) { - module->ant.type = BTC_ANT_SHARED; - module->bt_pos = BTC_BT_BTG; - module->wa_type = 1; - module->ant.diversity = 0; - } else { /* ant.num == 2 */ - module->ant.type = BTC_ANT_DEDICATED; - module->bt_pos = BTC_BT_ALONE; - module->switch_type = BTC_SWITCH_EXTERNAL; - module->wa_type = 0; - if (module->rfe_type % 3 == 2) - module->ant.diversity = 1; + const struct rtw89_btc_ver *ver = rtwdev->btc.ver; + union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; + + if (ver->fcxinit == 7) { + md->md_v7.rfe_type = rtwdev->efuse.rfe_type; + md->md_v7.kt_ver = rtwdev->hal.cv; + md->md_v7.bt_solo = 0; + md->md_v7.switch_type = BTC_SWITCH_INTERNAL; + md->md_v7.ant.isolation = 10; + md->md_v7.kt_ver_adie = rtwdev->hal.acv; + + if (md->md_v7.rfe_type == 0) + return; + + /* rfe_type 3*n+1: 1-Ant(shared), + * 3*n+2: 2-Ant+Div(non-shared), + * 3*n+3: 2-Ant+no-Div(non-shared) + */ + md->md_v7.ant.num = (md->md_v7.rfe_type % 3 == 1) ? 1 : 2; + /* WL-1ss at S0, btg at s0 (On 1 WL RF) */ + md->md_v7.ant.single_pos = RF_PATH_A; + md->md_v7.ant.btg_pos = RF_PATH_A; + md->md_v7.ant.stream_cnt = 1; + + if (md->md_v7.ant.num == 1) { + md->md_v7.ant.type = BTC_ANT_SHARED; + md->md_v7.bt_pos = BTC_BT_BTG; + md->md_v7.wa_type = 1; + md->md_v7.ant.diversity = 0; + } else { /* ant.num == 2 */ + md->md_v7.ant.type = BTC_ANT_DEDICATED; + md->md_v7.bt_pos = BTC_BT_ALONE; + md->md_v7.switch_type = BTC_SWITCH_EXTERNAL; + md->md_v7.wa_type = 0; + if (md->md_v7.rfe_type % 3 == 2) + md->md_v7.ant.diversity = 1; + } + rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; + rtwdev->btc.ant_type = md->md_v7.ant.type; + } else { + md->md.rfe_type = rtwdev->efuse.rfe_type; + md->md.cv = rtwdev->hal.cv; + md->md.bt_solo = 0; + md->md.switch_type = BTC_SWITCH_INTERNAL; + md->md.ant.isolation = 10; + md->md.kt_ver_adie = rtwdev->hal.acv; + + if (md->md.rfe_type == 0) + return; + + /* rfe_type 3*n+1: 1-Ant(shared), + * 3*n+2: 2-Ant+Div(non-shared), + * 3*n+3: 2-Ant+no-Div(non-shared) + */ + md->md.ant.num = (md->md.rfe_type % 3 == 1) ? 1 : 2; + /* WL-1ss at S0, btg at s0 (On 1 WL RF) */ + md->md.ant.single_pos = RF_PATH_A; + md->md.ant.btg_pos = RF_PATH_A; + md->md.ant.stream_cnt = 1; + + if (md->md.ant.num == 1) { + md->md.ant.type = BTC_ANT_SHARED; + md->md.bt_pos = BTC_BT_BTG; + md->md.wa_type = 1; + md->md.ant.diversity = 0; + } else { /* ant.num == 2 */ + md->md.ant.type = BTC_ANT_DEDICATED; + md->md.bt_pos = BTC_BT_ALONE; + md->md.switch_type = BTC_SWITCH_EXTERNAL; + md->md.wa_type = 0; + if (md->md.rfe_type % 3 == 2) + md->md.ant.diversity = 1; + } + rtwdev->btc.btg_pos = md->md.ant.btg_pos; + rtwdev->btc.ant_type = md->md.ant.type; } } @@ -1965,7 +2005,7 @@ void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) if (group > BTC_BT_SS_GROUP) group--; /* Tx-group=1, Rx-group=2 */ - if (rtwdev->btc.mdinfo.ant.type == BTC_ANT_SHARED) /* 1-Ant */ + if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */ group += 3; rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); @@ -1980,9 +2020,9 @@ static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev) }; const struct rtw89_chip_info *chip = rtwdev->chip; struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; - struct rtw89_btc_ant_info *ant = &module->ant; - u8 path, path_min, path_max; + union rtw89_btc_module_info *md = &btc->mdinfo; + const struct rtw89_btc_ver *ver = btc->ver; + u8 path, path_min, path_max, str_cnt, ant_sing_pos; /* PTA init */ rtw89_mac_coex_init(rtwdev, &coex_params); @@ -1991,9 +2031,17 @@ static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev) chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); + if (ver->fcxinit == 7) { + str_cnt = md->md_v7.ant.stream_cnt; + ant_sing_pos = md->md_v7.ant.single_pos; + } else { + str_cnt = md->md.ant.stream_cnt; + ant_sing_pos = md->md.ant.single_pos; + } + /* for 1-Ant && 1-ss case: only 1-path */ - if (ant->stream_cnt == 1) { - path_min = ant->single_pos; + if (str_cnt == 1) { + path_min = ant_sing_pos; path_max = path_min; } else { path_min = RF_PATH_A; @@ -2016,7 +2064,7 @@ static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev) /* if GNT_WL = 0 && BT = Tx_group --> * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) */ - if (ant->type == BTC_ANT_SHARED && ant->btg_pos == path) + if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path) rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f); else rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); @@ -2148,19 +2196,18 @@ void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev) static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) { struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant; - rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000); - rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWA, RFREG_MASK, 0x1); - rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110); + rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000); + rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1); + rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110); /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ if (state) - rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c); + rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c); else - rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208); + rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208); - rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x0); + rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0); } #define LNA2_51B_MA 0x700 @@ -2175,7 +2222,6 @@ static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB */ struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant; const struct rtw89_reg2_def *rf; u32 n, i, val; @@ -2203,10 +2249,10 @@ static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) for (i = 0; i < n; i++, rf++) { val = rf->data; /* bit[10] = 1 if non-shared-ant for 8851b */ - if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED) + if (btc->ant_type == BTC_ANT_DEDICATED) val |= 0x4; - rtw89_write_rf(rtwdev, ant->btg_pos, rf->addr, LNA2_51B_MA, val); + rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val); } } @@ -2460,6 +2506,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = { .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, .c2h_regs = rtw8851b_c2h_regs, .page_regs = &rtw8851b_page_regs, + .wow_reason_reg = R_AX_C2HREG_DATA3 + 3, .cfo_src_fd = true, .cfo_hw_comp = true, .dcfo_comp = &rtw8851b_dcfo_comp, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c index 8e808ded5d52..2deadec715cf 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c @@ -1665,28 +1665,55 @@ static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) { - struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; + const struct rtw89_btc_ver *ver = rtwdev->btc.ver; + union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; - module->rfe_type = rtwdev->efuse.rfe_type; - module->cv = rtwdev->hal.cv; - module->bt_solo = 0; - module->switch_type = BTC_SWITCH_INTERNAL; + if (ver->fcxinit == 7) { + md->md_v7.rfe_type = rtwdev->efuse.rfe_type; + md->md_v7.kt_ver = rtwdev->hal.cv; + md->md_v7.bt_solo = 0; + md->md_v7.switch_type = BTC_SWITCH_INTERNAL; - if (module->rfe_type > 0) - module->ant.num = (module->rfe_type % 2 ? 2 : 3); - else - module->ant.num = 2; + if (md->md_v7.rfe_type > 0) + md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); + else + md->md_v7.ant.num = 2; - module->ant.diversity = 0; - module->ant.isolation = 10; + md->md_v7.ant.diversity = 0; + md->md_v7.ant.isolation = 10; - if (module->ant.num == 3) { - module->ant.type = BTC_ANT_DEDICATED; - module->bt_pos = BTC_BT_ALONE; + if (md->md_v7.ant.num == 3) { + md->md_v7.ant.type = BTC_ANT_DEDICATED; + md->md_v7.bt_pos = BTC_BT_ALONE; + } else { + md->md_v7.ant.type = BTC_ANT_SHARED; + md->md_v7.bt_pos = BTC_BT_BTG; + } + rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; + rtwdev->btc.ant_type = md->md_v7.ant.type; } else { - module->ant.type = BTC_ANT_SHARED; - module->bt_pos = BTC_BT_BTG; + md->md.rfe_type = rtwdev->efuse.rfe_type; + md->md.cv = rtwdev->hal.cv; + md->md.bt_solo = 0; + md->md.switch_type = BTC_SWITCH_INTERNAL; + + if (md->md.rfe_type > 0) + md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); + else + md->md.ant.num = 2; + + md->md.ant.diversity = 0; + md->md.ant.isolation = 10; + + if (md->md.ant.num == 3) { + md->md.ant.type = BTC_ANT_DEDICATED; + md->md.bt_pos = BTC_BT_ALONE; + } else { + md->md.ant.type = BTC_ANT_SHARED; + md->md.bt_pos = BTC_BT_BTG; + } + rtwdev->btc.btg_pos = md->md.ant.btg_pos; + rtwdev->btc.ant_type = md->md.ant.type; } } @@ -1717,7 +1744,6 @@ static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) { struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; const struct rtw89_chip_info *chip = rtwdev->chip; const struct rtw89_mac_ax_coex coex_params = { .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, @@ -1736,7 +1762,7 @@ static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ - if (module->ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { rtw8852a_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); rtw8852a_set_trx_mask(rtwdev, @@ -2197,6 +2223,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = { .c2h_regs = rtw8852a_c2h_regs, .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, .page_regs = &rtw8852a_page_regs, + .wow_reason_reg = R_AX_C2HREG_DATA3 + 3, .cfo_src_fd = false, .cfo_hw_comp = false, .dcfo_comp = &rtw8852a_dcfo_comp, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c index 19454766f3de..d025c4135e1c 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c @@ -2125,28 +2125,55 @@ static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) { - struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; + const struct rtw89_btc_ver *ver = rtwdev->btc.ver; + union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; - module->rfe_type = rtwdev->efuse.rfe_type; - module->cv = rtwdev->hal.cv; - module->bt_solo = 0; - module->switch_type = BTC_SWITCH_INTERNAL; + if (ver->fcxinit == 7) { + md->md_v7.rfe_type = rtwdev->efuse.rfe_type; + md->md_v7.kt_ver = rtwdev->hal.cv; + md->md_v7.bt_solo = 0; + md->md_v7.switch_type = BTC_SWITCH_INTERNAL; - if (module->rfe_type > 0) - module->ant.num = module->rfe_type % 2 ? 2 : 3; - else - module->ant.num = 2; + if (md->md_v7.rfe_type > 0) + md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); + else + md->md_v7.ant.num = 2; - module->ant.diversity = 0; - module->ant.isolation = 10; + md->md_v7.ant.diversity = 0; + md->md_v7.ant.isolation = 10; - if (module->ant.num == 3) { - module->ant.type = BTC_ANT_DEDICATED; - module->bt_pos = BTC_BT_ALONE; + if (md->md_v7.ant.num == 3) { + md->md_v7.ant.type = BTC_ANT_DEDICATED; + md->md_v7.bt_pos = BTC_BT_ALONE; + } else { + md->md_v7.ant.type = BTC_ANT_SHARED; + md->md_v7.bt_pos = BTC_BT_BTG; + } + rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; + rtwdev->btc.ant_type = md->md_v7.ant.type; } else { - module->ant.type = BTC_ANT_SHARED; - module->bt_pos = BTC_BT_BTG; + md->md.rfe_type = rtwdev->efuse.rfe_type; + md->md.cv = rtwdev->hal.cv; + md->md.bt_solo = 0; + md->md.switch_type = BTC_SWITCH_INTERNAL; + + if (md->md.rfe_type > 0) + md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); + else + md->md.ant.num = 2; + + md->md.ant.diversity = 0; + md->md.ant.isolation = 10; + + if (md->md.ant.num == 3) { + md->md.ant.type = BTC_ANT_DEDICATED; + md->md.bt_pos = BTC_BT_ALONE; + } else { + md->md.ant.type = BTC_ANT_SHARED; + md->md.bt_pos = BTC_BT_BTG; + } + rtwdev->btc.btg_pos = md->md.ant.btg_pos; + rtwdev->btc.ant_type = md->md.ant.type; } } @@ -2162,7 +2189,6 @@ void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev) { struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; const struct rtw89_chip_info *chip = rtwdev->chip; const struct rtw89_mac_ax_coex coex_params = { .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, @@ -2181,7 +2207,7 @@ static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev) rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ - if (module->ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ @@ -2631,6 +2657,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = { .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, .c2h_regs = rtw8852b_c2h_regs, .page_regs = &rtw8852b_page_regs, + .wow_reason_reg = R_AX_C2HREG_DATA3 + 3, .cfo_src_fd = true, .cfo_hw_comp = true, .dcfo_comp = &rtw8852b_dcfo_comp, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c.c b/drivers/net/wireless/realtek/rtw89/rtw8852c.c index ca8547fbd70e..17e6164855fa 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852c.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852c.c @@ -2365,28 +2365,55 @@ static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) { - struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; + const struct rtw89_btc_ver *ver = rtwdev->btc.ver; + union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; - module->rfe_type = rtwdev->efuse.rfe_type; - module->cv = rtwdev->hal.cv; - module->bt_solo = 0; - module->switch_type = BTC_SWITCH_INTERNAL; + if (ver->fcxinit == 7) { + md->md_v7.rfe_type = rtwdev->efuse.rfe_type; + md->md_v7.kt_ver = rtwdev->hal.cv; + md->md_v7.bt_solo = 0; + md->md_v7.switch_type = BTC_SWITCH_INTERNAL; - if (module->rfe_type > 0) - module->ant.num = (module->rfe_type % 2 ? 2 : 3); - else - module->ant.num = 2; + if (md->md_v7.rfe_type > 0) + md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); + else + md->md_v7.ant.num = 2; - module->ant.diversity = 0; - module->ant.isolation = 10; + md->md_v7.ant.diversity = 0; + md->md_v7.ant.isolation = 10; - if (module->ant.num == 3) { - module->ant.type = BTC_ANT_DEDICATED; - module->bt_pos = BTC_BT_ALONE; + if (md->md_v7.ant.num == 3) { + md->md_v7.ant.type = BTC_ANT_DEDICATED; + md->md_v7.bt_pos = BTC_BT_ALONE; + } else { + md->md_v7.ant.type = BTC_ANT_SHARED; + md->md_v7.bt_pos = BTC_BT_BTG; + } + rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; + rtwdev->btc.ant_type = md->md_v7.ant.type; } else { - module->ant.type = BTC_ANT_SHARED; - module->bt_pos = BTC_BT_BTG; + md->md.rfe_type = rtwdev->efuse.rfe_type; + md->md.cv = rtwdev->hal.cv; + md->md.bt_solo = 0; + md->md.switch_type = BTC_SWITCH_INTERNAL; + + if (md->md.rfe_type > 0) + md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); + else + md->md.ant.num = 2; + + md->md.ant.diversity = 0; + md->md.ant.isolation = 10; + + if (md->md.ant.num == 3) { + md->md.ant.type = BTC_ANT_DEDICATED; + md->md.bt_pos = BTC_BT_ALONE; + } else { + md->md.ant.type = BTC_ANT_SHARED; + md->md.bt_pos = BTC_BT_BTG; + } + rtwdev->btc.btg_pos = md->md.ant.btg_pos; + rtwdev->btc.ant_type = md->md.ant.type; } } @@ -2449,7 +2476,6 @@ void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) { struct rtw89_btc *btc = &rtwdev->btc; - struct rtw89_btc_module *module = &btc->mdinfo; const struct rtw89_chip_info *chip = rtwdev->chip; const struct rtw89_mac_ax_coex coex_params = { .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, @@ -2468,7 +2494,7 @@ static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ - if (module->ant.type == BTC_ANT_SHARED) { + if (btc->ant_type == BTC_ANT_SHARED) { rtw8852c_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); rtw8852c_set_trx_mask(rtwdev, @@ -2971,6 +2997,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = { .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, .c2h_regs = rtw8852c_c2h_regs, .page_regs = &rtw8852c_page_regs, + .wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3, .cfo_src_fd = false, .cfo_hw_comp = false, .dcfo_comp = &rtw8852c_dcfo_comp, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8922a.c b/drivers/net/wireless/realtek/rtw89/rtw8922a.c index 823f0d840df9..367459bd1345 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8922a.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8922a.c @@ -2150,6 +2150,113 @@ static u8 rtw8922a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p return clamp_t(int, th, 0, U8_MAX); } +static void rtw8922a_btc_set_rfe(struct rtw89_dev *rtwdev) +{ + union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; + struct rtw89_btc_module_v7 *module = &md->md_v7; + + module->rfe_type = rtwdev->efuse.rfe_type; + module->kt_ver = rtwdev->hal.cv; + module->bt_solo = 0; + module->switch_type = BTC_SWITCH_INTERNAL; + module->wa_type = 0; + + module->ant.type = BTC_ANT_SHARED; + module->ant.num = 2; + module->ant.isolation = 10; + module->ant.diversity = 0; + module->ant.single_pos = RF_PATH_A; + module->ant.btg_pos = RF_PATH_B; + + if (module->kt_ver <= 1) + module->wa_type |= BTC_WA_HFP_ZB; + + rtwdev->btc.cx.other.type = BTC_3CX_NONE; + + if (module->rfe_type == 0) { + rtwdev->btc.dm.error.map.rfe_type0 = true; + return; + } + + module->ant.num = (module->rfe_type % 2) ? 2 : 3; + + if (module->kt_ver == 0) + module->ant.num = 2; + + if (module->ant.num == 3) { + module->ant.type = BTC_ANT_DEDICATED; + module->bt_pos = BTC_BT_ALONE; + } else { + module->ant.type = BTC_ANT_SHARED; + module->bt_pos = BTC_BT_BTG; + } + rtwdev->btc.btg_pos = module->ant.btg_pos; + rtwdev->btc.ant_type = module->ant.type; +} + +static +void rtw8922a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) +{ + rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); + rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); +} + +static void rtw8922a_btc_init_cfg(struct rtw89_dev *rtwdev) +{ + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_ant_info_v7 *ant = &btc->mdinfo.md_v7.ant; + u32 wl_pri, path_min, path_max; + u8 path; + + /* for 1-Ant && 1-ss case: only 1-path */ + if (ant->num == 1) { + path_min = ant->single_pos; + path_max = path_min; + } else { + path_min = RF_PATH_A; + path_max = RF_PATH_B; + } + + path = path_min; + + for (path = path_min; path <= path_max; path++) { + /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */ + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17)); + + /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */ + rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff); + + /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */ + rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df); + + /* if GNT_WL = 0 && BT = Tx_group --> + * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) + */ + if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path) + rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); + else + rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); + + rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0); + } + + /* set WL PTA Hi-Pri: Ack-Tx, beacon-tx, Trig-frame-Tx, Null-Tx*/ + wl_pri = B_BTC_RSP_ACK_HI | B_BTC_TX_BCN_HI | B_BTC_TX_TRI_HI | + B_BTC_TX_NULL_HI; + rtw89_write32(rtwdev, R_BTC_COEX_WL_REQ_BE, wl_pri); + + /* set PTA break table */ + rtw89_write32(rtwdev, R_BE_BT_BREAK_TABLE, BTC_BREAK_PARAM); + + /* ZB coex table init for HFP PTA req-cmd bit-4 define issue COEX-900*/ + rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, 0xda5a5a5a); + + rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, 0xda5a5a5a); + + rtw89_write32(rtwdev, R_BTC_ZB_BREAK_TBL, 0xf0ffffff); + btc->cx.wl.status.map.init_ok = true; +} + static void rtw8922a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, struct rtw89_rx_phy_ppdu *phy_ppdu, struct ieee80211_rx_status *status) @@ -2246,6 +2353,8 @@ static const struct rtw89_chip_ops rtw8922a_chip_ops = { .query_rxdesc = rtw89_core_query_rxdesc_v2, .fill_txdesc = rtw89_core_fill_txdesc_v2, .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v2, + .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v2, + .mac_cfg_gnt = rtw89_mac_cfg_gnt_v2, .stop_sch_tx = rtw89_mac_stop_sch_tx_v2, .resume_sch_tx = rtw89_mac_resume_sch_tx_v2, .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v2, @@ -2255,6 +2364,9 @@ static const struct rtw89_chip_ops rtw8922a_chip_ops = { .h2c_default_dmac_tbl = rtw89_fw_h2c_default_dmac_tbl_v2, .h2c_update_beacon = rtw89_fw_h2c_update_beacon_be, .h2c_ba_cam = rtw89_fw_h2c_ba_cam_v1, + + .btc_set_rfe = rtw8922a_btc_set_rfe, + .btc_init_cfg = rtw8922a_btc_init_cfg, }; const struct rtw89_chip_info rtw8922a_chip_info = { @@ -2341,6 +2453,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = { .c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, .c2h_regs = rtw8922a_c2h_regs, .page_regs = &rtw8922a_page_regs, + .wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3, .cfo_src_fd = true, .cfo_hw_comp = true, .dcfo_comp = NULL, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8922ae.c b/drivers/net/wireless/realtek/rtw89/rtw8922ae.c index 9f46fb166105..4981b657bd7b 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8922ae.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8922ae.c @@ -80,7 +80,7 @@ static struct pci_driver rtw89_8922ae_driver = { .id_table = rtw89_8922ae_id_table, .probe = rtw89_pci_probe, .remove = rtw89_pci_remove, - .driver.pm = &rtw89_pm_ops, + .driver.pm = &rtw89_pm_ops_be, }; module_pci_driver(rtw89_8922ae_driver); diff --git a/drivers/net/wireless/realtek/rtw89/wow.c b/drivers/net/wireless/realtek/rtw89/wow.c index 4c17936795b6..ccad026defb5 100644 --- a/drivers/net/wireless/realtek/rtw89/wow.c +++ b/drivers/net/wireless/realtek/rtw89/wow.c @@ -41,34 +41,8 @@ static void rtw89_wow_leave_lps(struct rtw89_dev *rtwdev) static int rtw89_wow_config_mac(struct rtw89_dev *rtwdev, bool enable_wow) { const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; - int ret; - - if (enable_wow) { - ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); - if (ret) { - rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); - return ret; - } - rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); - rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); - rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); - rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); - rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); - rtw89_write32(rtwdev, R_AX_TF_FWD, 0); - rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); - } else { - ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); - if (ret) { - rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); - return ret; - } - rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); - rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); - rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); - rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); - } - return 0; + return mac->wow_config_mac(rtwdev, enable_wow); } static void rtw89_wow_set_rx_filter(struct rtw89_dev *rtwdev, bool enable) @@ -85,21 +59,14 @@ static void rtw89_wow_set_rx_filter(struct rtw89_dev *rtwdev, bool enable) static void rtw89_wow_show_wakeup_reason(struct rtw89_dev *rtwdev) { - enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; + u32 wow_reason_reg = rtwdev->chip->wow_reason_reg; struct cfg80211_wowlan_nd_info nd_info; struct cfg80211_wowlan_wakeup wakeup = { .pattern_idx = -1, }; - u32 wow_reason_reg; u8 reason; - if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B) - wow_reason_reg = R_AX_C2HREG_DATA3 + 3; - else - wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3; - reason = rtw89_read8(rtwdev, wow_reason_reg); - switch (reason) { case RTW89_WOW_RSN_RX_DEAUTH: wakeup.disconnect = true; @@ -470,13 +437,14 @@ static int rtw89_wow_cfg_wake(struct rtw89_dev *rtwdev, bool wow) static int rtw89_wow_check_fw_status(struct rtw89_dev *rtwdev, bool wow_enable) { + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; u8 polling; int ret; ret = read_poll_timeout_atomic(rtw89_read8_mask, polling, wow_enable == !!polling, 50, 50000, false, rtwdev, - R_AX_WOW_CTRL, B_AX_WOW_WOWEN); + mac->wow_ctrl.addr, mac->wow_ctrl.mask); if (ret) rtw89_err(rtwdev, "failed to check wow status %s\n", wow_enable ? "enabled" : "disabled"); @@ -566,7 +534,7 @@ static int rtw89_wow_enable_trx_pre(struct rtw89_dev *rtwdev) rtw89_mac_ptk_drop_by_band_and_wait(rtwdev, RTW89_MAC_0); - ret = rtw89_hci_poll_txdma_ch(rtwdev); + ret = rtw89_hci_poll_txdma_ch_idle(rtwdev); if (ret) { rtw89_err(rtwdev, "txdma ch busy\n"); return ret; @@ -589,7 +557,7 @@ static int rtw89_wow_enable_trx_post(struct rtw89_dev *rtwdev) rtw89_hci_disable_intr(rtwdev); rtw89_hci_ctrl_trxhci(rtwdev, false); - ret = rtw89_hci_poll_txdma_ch(rtwdev); + ret = rtw89_hci_poll_txdma_ch_idle(rtwdev); if (ret) { rtw89_err(rtwdev, "failed to poll txdma ch idle pcie\n"); return ret; @@ -699,14 +667,14 @@ static int rtw89_wow_fw_stop(struct rtw89_dev *rtwdev) goto out; } + rtw89_fw_release_general_pkt_list(rtwdev, true); + ret = rtw89_wow_cfg_wake(rtwdev, false); if (ret) { rtw89_err(rtwdev, "wow: failed to disable config wake\n"); goto out; } - rtw89_fw_release_general_pkt_list(rtwdev, true); - ret = rtw89_wow_check_fw_status(rtwdev, false); if (ret) { rtw89_err(rtwdev, "wow: failed to check disable fw ready\n"); |