summaryrefslogtreecommitdiff
path: root/drivers/ntb/hw
diff options
context:
space:
mode:
authorSerge Semin <fancer.lancer@gmail.com>2018-07-11 23:40:51 +0300
committerJon Mason <jdmason@kudzu.us>2018-11-01 04:20:05 +0300
commit37a3e9693d444701e4b8f8b98ee0480450bb5982 (patch)
tree103f602cbef18b12705cdd0e4b8f9d4edad867f9 /drivers/ntb/hw
parent1b7619828d0c341612f58683e73f279c37e70bbc (diff)
downloadlinux-37a3e9693d444701e4b8f8b98ee0480450bb5982.tar.xz
ntb: idt: Set PCIe bus address to BARLIMITx
IDT NTB driver sets the upper limit of actual translation address being written to the corresponding memory window setup. It is achieved by BARLIMITx register initialization. Needless to say, that the register works within PCIe bus address space. In general CPU and PCIe address spaces are different. It means, that addresses used for Memory TLPs routine can be different from CPU addresses. While in most of cases they are the same, there are exceptions when the proper mapping must be performed to have the portable driver code. There used to be a virt_to_bus()/bus_to_virt() interface for this purpose. But it's deprecated now. It was also a mistake to use pci_resource_start() since the return address of the method is at the CPU address space. In order to achieve the desired purpose we need to use pci_bus_address() helper. This method shall return a PCIe bus base address of the corresponding BAR resource. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Allen Hubbe <allenbh@gmail.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'drivers/ntb/hw')
-rw-r--r--drivers/ntb/hw/idt/ntb_hw_idt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c
index a67ef23e81bc..54485a8d2d7f 100644
--- a/drivers/ntb/hw/idt/ntb_hw_idt.c
+++ b/drivers/ntb/hw/idt/ntb_hw_idt.c
@@ -1320,7 +1320,7 @@ static int idt_ntb_peer_mw_set_trans(struct ntb_dev *ntb, int pidx, int widx,
idt_nt_write(ndev, bar->ltbase, (u32)addr);
idt_nt_write(ndev, bar->utbase, (u32)(addr >> 32));
/* Set the custom BAR aperture limit */
- limit = pci_resource_start(ntb->pdev, mw_cfg->bar) + size;
+ limit = pci_bus_address(ntb->pdev, mw_cfg->bar) + size;
idt_nt_write(ndev, bar->limit, (u32)limit);
if (IS_FLD_SET(BARSETUP_TYPE, data, 64))
idt_nt_write(ndev, (bar + 1)->limit, (limit >> 32));