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authorSerge Semin <Sergey.Semin@baikalelectronics.ru>2022-06-24 17:39:35 +0300
committerBjorn Helgaas <bhelgaas@google.com>2022-08-01 23:01:57 +0300
commitafe1c6d50d33ea7d888b0105670fb2aaa5abf495 (patch)
treef3b5ed3b8de07cde170b8befd9f68c7c5ac2f62e /drivers/pci/controller/dwc/pcie-designware.c
parente3dc79adfac96d7b1a62f3f27004c3f9013875bc (diff)
downloadlinux-afe1c6d50d33ea7d888b0105670fb2aaa5abf495.tar.xz
PCI: dwc: Use native DWC IP core version representation
Save the DWC IP core version in the same format as the PORT_LOGIC.PCIE_VERSION_OFF register, similar to what other drivers for DWC IP do (dw_spi_hw_init(), dwc3_core_is_valid(), stmmac_hwif_init()). [bhelgaas: trim commit log] Link: https://lore.kernel.org/r/20220624143947.8991-4-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.c')
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index e66d16a86168..f10a7d5d94e8 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -289,7 +289,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
val = type | PCIE_ATU_FUNC_NUM(func_no);
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr))
val |= PCIE_ATU_INCREASE_REGION_SIZE;
- if (pci->version == 0x490A)
+ if (pci->version == DW_PCIE_VER_490A)
val = dw_pcie_enable_ecrc(val);
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
@@ -336,7 +336,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
upper_32_bits(cpu_addr));
dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
lower_32_bits(limit_addr));
- if (pci->version >= 0x460A)
+ if (pci->version >= DW_PCIE_VER_460A)
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
upper_32_bits(limit_addr));
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
@@ -345,9 +345,9 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
upper_32_bits(pci_addr));
val = type | PCIE_ATU_FUNC_NUM(func_no);
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
- pci->version >= 0x460A)
+ pci->version >= DW_PCIE_VER_460A)
val |= PCIE_ATU_INCREASE_REGION_SIZE;
- if (pci->version == 0x490A)
+ if (pci->version == DW_PCIE_VER_490A)
val = dw_pcie_enable_ecrc(val);
dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);