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authorGustavo Pimentel <gustavo.pimentel@synopsys.com>2018-03-06 14:54:55 +0300
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-03-06 17:31:16 +0300
commit1f319cb0538a10339d1ca73ee124331d611b43bf (patch)
treeccd78704d15da4482172c0df4ff3511fd8923802 /drivers/pci/dwc/pcie-designware.h
parent3f43ccc4ea1b912ff24679576b4278fafbb190b3 (diff)
downloadlinux-1f319cb0538a10339d1ca73ee124331d611b43bf.tar.xz
PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256
The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed over 8 controller registers, therefore the maximum number of MSI IRQs can be changed to 256. The number of controllers can be calculated based on the number of vectors used by the specific SoC driver. Update the dwc host bridge driver maximum number of supported MSI IRQs. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/pci/dwc/pcie-designware.h')
-rw-r--r--drivers/pci/dwc/pcie-designware.h10
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 923f9565a385..fe811dbc12cf 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -107,13 +107,9 @@
#define MSI_MESSAGE_DATA_32 0x58
#define MSI_MESSAGE_DATA_64 0x5C
-/*
- * Maximum number of MSI IRQs can be 256 per controller. But keep
- * it 32 as of now. Probably we will never need more than 32. If needed,
- * then increment it in multiple of 32.
- */
-#define MAX_MSI_IRQS 32
-#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
+#define MAX_MSI_IRQS 256
+#define MAX_MSI_IRQS_PER_CTRL 32
+#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
#define MSI_DEF_NUM_VECTORS 32
/* Maximum number of inbound/outbound iATUs */