summaryrefslogtreecommitdiff
path: root/drivers/pci/pci.c
diff options
context:
space:
mode:
authorMika Westerberg <mika.westerberg@linux.intel.com>2023-04-04 23:32:55 +0300
committerBjorn Helgaas <bhelgaas@google.com>2023-04-12 01:35:06 +0300
commite74b2b58ff715ca17bb49c3ad89f665a7150e14b (patch)
tree29be645c6f56e6cdf9a9bbb8a9f97ea1a178f392 /drivers/pci/pci.c
parente8b908146d44310473e43b3382eca126e12d279c (diff)
downloadlinux-e74b2b58ff715ca17bb49c3ad89f665a7150e14b.tar.xz
PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter
All callers of pci_bridge_wait_for_secondary_bus() supply a timeout of PCIE_RESET_READY_POLL_MS, so drop the parameter. Move the definition of PCIE_RESET_READY_POLL_MS into pci.c, the only user. [bhelgaas: extracted from https://lore.kernel.org/r/20230404052714.51315-3-mika.westerberg@linux.intel.com] Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7a67611dc5f4..0b4f3b08f780 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -64,6 +64,14 @@ struct pci_pme_device {
#define PME_TIMEOUT 1000 /* How long between PME checks */
+/*
+ * Devices may extend the 1 sec period through Request Retry Status
+ * completions (PCIe r6.0 sec 2.3.1). The spec does not provide an upper
+ * limit, but 60 sec ought to be enough for any device to become
+ * responsive.
+ */
+#define PCIE_RESET_READY_POLL_MS 60000 /* msec */
+
static void pci_dev_d3_sleep(struct pci_dev *dev)
{
unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
@@ -4939,7 +4947,6 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
* pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
* @dev: PCI bridge
* @reset_type: reset type in human-readable form
- * @timeout: maximum time to wait for devices on secondary bus (milliseconds)
*
* Handle necessary delays before access to the devices on the secondary
* side of the bridge are permitted after D3cold to D0 transition
@@ -4952,8 +4959,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
* Return 0 on success or -ENOTTY if the first device on the secondary bus
* failed to become accessible.
*/
-int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
- int timeout)
+int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)
{
struct pci_dev *child;
int delay;
@@ -5031,7 +5037,8 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
}
}
- return pci_dev_wait(child, reset_type, timeout - delay);
+ return pci_dev_wait(child, reset_type,
+ PCIE_RESET_READY_POLL_MS - delay);
}
void pci_reset_secondary_bus(struct pci_dev *dev)
@@ -5068,8 +5075,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
{
pcibios_reset_secondary_bus(dev);
- return pci_bridge_wait_for_secondary_bus(dev, "bus reset",
- PCIE_RESET_READY_POLL_MS);
+ return pci_bridge_wait_for_secondary_bus(dev, "bus reset");
}
EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);