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authorBjorn Helgaas <bhelgaas@google.com>2023-02-22 22:47:27 +0300
committerBjorn Helgaas <bhelgaas@google.com>2023-02-22 22:47:27 +0300
commit0b7af1ddcf62e6f497b26e967a65dad5d46d79ae (patch)
tree136b6535ed78101128a468f4b64af229d3fe4cf9 /drivers/pci/pci.h
parent08a67024a0b4a18b2fad8d5b3670f02e9b24ebfb (diff)
parent53b54ad074de1896f8b021615f65b27f557ce874 (diff)
downloadlinux-0b7af1ddcf62e6f497b26e967a65dad5d46d79ae.tar.xz
Merge branch 'pci/reset'
- Always observe reset delay when waking devices from D3cold, e.g., after system sleep, regardless of whether we're allowed to runtime-suspend to D3cold (Lukas Wunner) - Unify reset and resume delays to wait for downstream devices after a bridge reset (Lukas Wunner) - Wait for downstream devices after a DPC-induced bridge reset (Lukas Wunner) * pci/reset: PCI/DPC: Await readiness of secondary bus after reset PCI: Unify delay handling for reset and resume PCI/PM: Observe reset delay irrespective of bridge_d3
Diffstat (limited to 'drivers/pci/pci.h')
-rw-r--r--drivers/pci/pci.h16
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 5d5a44aaafe8..280e3675989c 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -64,6 +64,19 @@ struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
#define PCI_PM_D3HOT_WAIT 10 /* msec */
#define PCI_PM_D3COLD_WAIT 100 /* msec */
+/*
+ * Following exit from Conventional Reset, devices must be ready within 1 sec
+ * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
+ * Reset (PCIe r6.0 sec 5.8).
+ */
+#define PCI_RESET_WAIT 1000 /* msec */
+/*
+ * Devices may extend the 1 sec period through Request Retry Status completions
+ * (PCIe r6.0 sec 2.3.1). The spec does not provide an upper limit, but 60 sec
+ * ought to be enough for any device to become responsive.
+ */
+#define PCIE_RESET_READY_POLL_MS 60000 /* msec */
+
void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
void pci_refresh_power_state(struct pci_dev *dev);
int pci_power_up(struct pci_dev *dev);
@@ -86,8 +99,9 @@ void pci_msi_init(struct pci_dev *dev);
void pci_msix_init(struct pci_dev *dev);
bool pci_bridge_d3_possible(struct pci_dev *dev);
void pci_bridge_d3_update(struct pci_dev *dev);
-void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
+int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
+ int timeout);
static inline void pci_wakeup_event(struct pci_dev *dev)
{