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authorShaokun Zhang <zhangshaokun@hisilicon.com>2020-06-05 12:43:41 +0300
committerWill Deacon <will@kernel.org>2020-06-08 17:46:41 +0300
commit961abd78adcb4c72c343fcd9f9dc5e2ebbe9b448 (patch)
tree9023071443732d0e82847ccac71b77eb16f21617 /drivers/perf/hisilicon
parent91970bef48d68d06b2bb3f464b572ad50941f6a9 (diff)
downloadlinux-961abd78adcb4c72c343fcd9f9dc5e2ebbe9b448.tar.xz
drivers/perf: hisi: Fix wrong value for all counters enable
In L3C uncore PMU drivers, bit16 is used to control all counters enable & disable. Wrong value is given in the driver and its default value is 1'b1, it can work because each PMU counter has its own control bits too. Let's fix the wrong value. Fixes: 2940bc433370 ("perf: hisi: Add support for HiSilicon SoC L3C PMU driver") Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/1591350221-32275-1-git-send-email-zhangshaokun@hisilicon.com Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf/hisilicon')
-rw-r--r--drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
index 8dd1278bec04..7719ae4e2c56 100644
--- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
@@ -35,7 +35,7 @@
/* L3C has 8-counters */
#define L3C_NR_COUNTERS 0x8
-#define L3C_PERF_CTRL_EN 0x20000
+#define L3C_PERF_CTRL_EN 0x10000
#define L3C_EVTYPE_NONE 0xff
/*