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authorAnurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>2020-06-29 15:00:53 +0300
committerVinod Koul <vkoul@kernel.org>2020-06-29 16:18:00 +0300
commit4a33bea003144e217d8a3ae666f171dfc2e97bd6 (patch)
tree13089a517c27bdd3e448041fd6e463d45d0ba65d /drivers/phy/Makefile
parentcea0f76a483d1270ac6f6513964e3e75193dda48 (diff)
downloadlinux-4a33bea003144e217d8a3ae666f171dfc2e97bd6.tar.xz
phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/Makefile')
-rw-r--r--drivers/phy/Makefile3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 16e2622277d7..c27408e4daae 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,4 +28,5 @@ obj-y += allwinner/ \
socionext/ \
st/ \
tegra/ \
- ti/
+ ti/ \
+ xilinx/