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authorBjorn Andersson <bjorn.andersson@linaro.org>2019-08-06 03:42:56 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2019-08-26 14:50:04 +0300
commit14ced7e3a1ae9bed7051df3718c8c7b583854a5c (patch)
treea08480ed8bc2eae0916a311002ff22c9efbe3ec4 /drivers/phy/rockchip
parentbe0345b2cc1f3e6044409b274c61bc44d59f640d (diff)
downloadlinux-14ced7e3a1ae9bed7051df3718c8c7b583854a5c.tar.xz
phy: qcom-qmp: Correct ready status, again
Despite extensive testing of commit 885bd765963b ("phy: qcom-qmp: Correct READY_STATUS poll break condition") I failed to conclude that the PHYSTATUS bit of the PCS_STATUS register used in PCIe and USB3 falls as the PHY gets ready. Similar to the prior bug with UFS the code will generally get past the check before the transition and thereby "succeed". Correct the name of the register used PCIe and USB3 PHYs, replace mask_pcs_ready with a constant expression depending on the type of the PHY and check for the appropriate ready state. Cc: stable@vger.kernel.org Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Evan Green <evgreen@chromium.org> Cc: Niklas Cassel <niklas.cassel@linaro.org> Reported-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Fixes: 885bd765963b ("phy: qcom-qmp: Correct READY_STATUS poll break condition") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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