summaryrefslogtreecommitdiff
path: root/drivers/phy
diff options
context:
space:
mode:
authorSiddharth Vadapalli <s-vadapalli@ti.com>2023-03-09 09:35:13 +0300
committerVinod Koul <vkoul@kernel.org>2023-05-16 17:30:52 +0300
commit178b65152149628a59d9805c11b18527141a2b7b (patch)
tree2a67b9204f9dac0f2a4ef8111cd93fa9f1a132cb /drivers/phy
parent6a301188420ae53d8606ef4c5584fc015574e1f9 (diff)
downloadlinux-178b65152149628a59d9805c11b18527141a2b7b.tar.xz
phy: ti: gmii-sel: Enable SGMII mode for J7200
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/ti/phy-gmii-sel.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 5e16d8dd5bee..f3da6b020247 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -221,7 +221,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
- .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+ .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};